# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,qcs8300-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. QCS8300 Display MDSS

maintainers:
  - Yongxing Mou <yongxing.mou@oss.qualcomm.com>

description:
  QCS8300 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
  DPU display controller, DP interfaces and EDP etc.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    const: qcom,qcs8300-mdss

  clocks:
    items:
      - description: Display AHB
      - description: Display hf AXI
      - description: Display core

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 3

  interconnect-names:
    maxItems: 3

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        contains:
          const: qcom,qcs8300-dpu

  "^displayport-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        contains:
          const: qcom,qcs8300-dp

  "^dsi@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        contains:
          const: qcom,qcs8300-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        contains:
          enum:
            - qcom,qcs8300-dsi-phy-5nm
            - qcom,qcs8300-edp-phy

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interconnect/qcom,icc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
    #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    mdss: display-subsystem@ae00000 {
        compatible = "qcom,qcs8300-mdss";
        reg = <0x0ae00000 0x1000>;
        reg-names = "mdss";

        interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
                        <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY
                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
        interconnect-names = "mdp0-mem",
                             "mdp1-mem",
                             "cpu-cfg";

        resets = <&dispcc_core_bcr>;
        power-domains = <&dispcc_gdsc>;

        clocks = <&dispcc_ahb_clk>,
                 <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&dispcc_mdp_clk>;

        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        iommus = <&apps_smmu 0x1000 0x402>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "nrt_bus",
                          "iface",
                          "lut",
                          "core",
                          "vsync";

            assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
            assigned-clock-rates = <19200000>;
            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmhpd RPMHPD_MMCX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;
            ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                    reg = <0>;

                    dpu_intf0_out: endpoint {
                         remote-endpoint = <&mdss_dp0_in>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&mdss_dsi0_in>;
                    };
                };
            };

            mdp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-375000000 {
                    opp-hz = /bits/ 64 <375000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-500000000 {
                    opp-hz = /bits/ 64 <500000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };

                opp-575000000 {
                    opp-hz = /bits/ 64 <575000000>;
                    required-opps = <&rpmhpd_opp_turbo>;
                };

                opp-650000000 {
                    opp-hz = /bits/ 64 <650000000>;
                    required-opps = <&rpmhpd_opp_turbo_l1>;
                };
            };
        };

        dsi@ae94000 {
            compatible = "qcom,qcs8300-dsi-ctrl",
                         "qcom,sa8775p-dsi-ctrl",
                         "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";
            assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
                              <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
            phys = <&mdss_dsi0_phy>;

            operating-points-v2 = <&dsi0_opp_table>;
            power-domains = <&rpmhpd RPMHPD_MMCX>;

            vdda-supply = <&vreg_l5a>;

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    mdss0_dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    mdss0_dsi0_out: endpoint { };
                };
            };

            dsi0_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-358000000 {
                    opp-hz = /bits/ 64 <358000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };
            };
        };

        mdss_dsi0_phy: phy@ae94400 {
            compatible = "qcom,qcs8300-dsi-phy-5nm",
                         "qcom,sa8775p-dsi-phy-5nm";
            reg = <0x0ae94400 0x200>,
                  <0x0ae94600 0x280>,
                  <0x0ae94900 0x27c>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";

            vdds-supply = <&vreg_l4a>;
        };

        mdss_dp0_phy: phy@aec2a00 {
            compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";

            reg = <0x0aec2a00 0x200>,
                  <0x0aec2200 0xd0>,
                  <0x0aec2600 0xd0>,
                  <0x0aec2000 0x1c8>;

            clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
                     <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
            clock-names = "aux",
                          "cfg_ahb";

            #clock-cells = <1>;
            #phy-cells = <0>;

            vdda-phy-supply = <&vreg_l1c>;
            vdda-pll-supply = <&vreg_l4a>;
        };

        displayport-controller@af54000 {
            compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp";

            pinctrl-0 = <&dp_hot_plug_det>;
            pinctrl-names = "default";

            reg = <0xaf54000 0x104>,
                  <0xaf54200 0x0c0>,
                  <0xaf55000 0x770>,
                  <0xaf56000 0x09c>,
                  <0xaf57000 0x09c>,
                  <0xaf58000 0x09c>,
                  <0xaf59000 0x09c>,
                  <0xaf5a000 0x23c>,
                  <0xaf5b000 0x23c>;

            interrupt-parent = <&mdss>;
            interrupts = <12>;
            clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
            clock-names = "core_iface",
                          "core_aux",
                          "ctrl_link",
                          "ctrl_link_iface",
                          "stream_pixel",
                          "stream_1_pixel",
                          "stream_2_pixel",
                          "stream_3_pixel";
            assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
            assigned-clock-parents = <&mdss_dp0_phy 0>,
                                     <&mdss_dp0_phy 1>,
                                     <&mdss_dp0_phy 1>,
                                     <&mdss_dp0_phy 1>;
            phys = <&mdss_dp0_phy>;
            phy-names = "dp";
            operating-points-v2 = <&dp_opp_table>;
            power-domains = <&rpmhpd RPMHPD_MMCX>;

            #sound-dai-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;

                    mdss_dp0_in: endpoint {
                        remote-endpoint = <&dpu_intf0_out>;
                    };
                };

                port@1 {
                   reg = <1>;

                   mdss_dp_out: endpoint { };
                };
            };

            dp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-160000000 {
                    opp-hz = /bits/ 64 <160000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-270000000 {
                    opp-hz = /bits/ 64 <270000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-540000000 {
                    opp-hz = /bits/ 64 <540000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-810000000 {
                    opp-hz = /bits/ 64 <810000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };
    };
...
