# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/T2H / RZ/N2H ADC12

maintainers:
  - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>

description: |
  A/D Converter block is a successive approximation analog-to-digital converter
  with a 12-bit accuracy. Up to 16 analog input channels can be selected.
  Conversions can be performed in single or continuous mode. Result of the ADC
  is stored in a 16-bit data register corresponding to each channel.

properties:
  compatible:
    oneOf:
      - items:
          - const: renesas,r9a09g087-adc # RZ/N2H
          - const: renesas,r9a09g077-adc # RZ/T2H
      - items:
          - const: renesas,r9a09g077-adc # RZ/T2H

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: A/D scan end interrupt
      - description: A/D scan end interrupt for Group B
      - description: A/D scan end interrupt for Group C
      - description: Window A compare match
      - description: Window B compare match
      - description: Compare match
      - description: Compare mismatch

  interrupt-names:
    items:
      - const: adi
      - const: gbadi
      - const: gcadi
      - const: cmpai
      - const: cmpbi
      - const: wcmpm
      - const: wcmpum

  clocks:
    items:
      - description: Converter clock
      - description: Peripheral clock

  clock-names:
    items:
      - const: adclk
      - const: pclk

  power-domains:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  "#io-channel-cells":
    const: 1

patternProperties:
  "^channel@[0-9a-f]$":
    $ref: adc.yaml
    type: object
    description: The external channels which are connected to the ADC.

    properties:
      reg:
        description: The channel number.
        maximum: 15

    required:
      - reg

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    adc@80008000 {
      compatible = "renesas,r9a09g077-adc";
      reg = <0x80008000 0x400>;
      interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
      interrupt-names = "adi", "gbadi", "gcadi",
                        "cmpai", "cmpbi", "wcmpm", "wcmpum";
      clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
               <&cpg CPG_MOD 225>;
      clock-names = "adclk", "pclk";
      power-domains = <&cpg>;
      #address-cells = <1>;
      #size-cells = <0>;
      #io-channel-cells = <1>;

      channel@0 {
        reg = <0x0>;
      };
      channel@1 {
        reg = <0x1>;
      };
      channel@2 {
        reg = <0x2>;
      };
      channel@3 {
        reg = <0x3>;
      };
    };
