# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8650 Camera Subsystem (CAMSS)

maintainers:
  - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>

description:
  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.

properties:
  compatible:
    const: qcom,sm8650-camss

  reg:
    maxItems: 17

  reg-names:
    items:
      - const: csid_wrapper
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid_lite0
      - const: csid_lite1
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: csiphy4
      - const: csiphy5
      - const: vfe0
      - const: vfe1
      - const: vfe2
      - const: vfe_lite0
      - const: vfe_lite1

  clocks:
    maxItems: 33

  clock-names:
    items:
      - const: camnoc_axi
      - const: cpas_ahb
      - const: cpas_fast_ahb
      - const: cpas_vfe0
      - const: cpas_vfe1
      - const: cpas_vfe2
      - const: cpas_vfe_lite
      - const: csid
      - const: csiphy0
      - const: csiphy0_timer
      - const: csiphy1
      - const: csiphy1_timer
      - const: csiphy2
      - const: csiphy2_timer
      - const: csiphy3
      - const: csiphy3_timer
      - const: csiphy4
      - const: csiphy4_timer
      - const: csiphy5
      - const: csiphy5_timer
      - const: csiphy_rx
      - const: gcc_axi_hf
      - const: qdss_debug_xo
      - const: vfe0
      - const: vfe0_fast_ahb
      - const: vfe1
      - const: vfe1_fast_ahb
      - const: vfe2
      - const: vfe2_fast_ahb
      - const: vfe_lite
      - const: vfe_lite_ahb
      - const: vfe_lite_cphy_rx
      - const: vfe_lite_csid

  interrupts:
    maxItems: 16

  interrupt-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid_lite0
      - const: csid_lite1
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: csiphy4
      - const: csiphy5
      - const: vfe0
      - const: vfe1
      - const: vfe2
      - const: vfe_lite0
      - const: vfe_lite1

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: ahb
      - const: hf_mnoc

  iommus:
    maxItems: 3

  power-domains:
    items:
      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.

  power-domain-names:
    items:
      - const: ife0
      - const: ife1
      - const: ife2
      - const: top

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    description:
      CSI input ports.

    patternProperties:
      "^port@[0-5]$":
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false

        description:
          Input port for receiving CSI data from a CSIPHY.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

            required:
              - data-lanes

  vdd-csiphy01-0p9-supply:
    description:
      Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.

  vdd-csiphy01-1p2-supply:
    description:
      Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.

  vdd-csiphy24-0p9-supply:
    description:
      Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.

  vdd-csiphy24-1p2-supply:
    description:
      Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.

  vdd-csiphy35-0p9-supply:
    description:
      Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.

  vdd-csiphy35-1p2-supply:
    description:
      Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interconnects
  - interconnect-names
  - interrupts
  - interrupt-names
  - iommus
  - power-domains
  - power-domain-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sm8650-camcc.h>
    #include <dt-bindings/clock/qcom,sm8650-gcc.h>
    #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        isp@acb6000 {
            compatible = "qcom,sm8650-camss";
            reg = <0 0x0acb6000 0 0x1000>,
                  <0 0x0acb8000 0 0x1000>,
                  <0 0x0acba000 0 0x1000>,
                  <0 0x0acbc000 0 0x1000>,
                  <0 0x0accb000 0 0x1000>,
                  <0 0x0acd0000 0 0x1000>,
                  <0 0x0ace4000 0 0x2000>,
                  <0 0x0ace6000 0 0x2000>,
                  <0 0x0ace8000 0 0x2000>,
                  <0 0x0acea000 0 0x2000>,
                  <0 0x0acec000 0 0x2000>,
                  <0 0x0acee000 0 0x2000>,
                  <0 0x0ac62000 0 0xf000>,
                  <0 0x0ac71000 0 0xf000>,
                  <0 0x0ac80000 0 0xf000>,
                  <0 0x0accc000 0 0x2000>,
                  <0 0x0acd1000 0 0x2000>;
            reg-names = "csid_wrapper",
                        "csid0",
                        "csid1",
                        "csid2",
                        "csid_lite0",
                        "csid_lite1",
                        "csiphy0",
                        "csiphy1",
                        "csiphy2",
                        "csiphy3",
                        "csiphy4",
                        "csiphy5",
                        "vfe0",
                        "vfe1",
                        "vfe2",
                        "vfe_lite0",
                        "vfe_lite1";
            clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
                     <&camcc CAM_CC_CPAS_AHB_CLK>,
                     <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
                     <&camcc CAM_CC_CPAS_IFE_0_CLK>,
                     <&camcc CAM_CC_CPAS_IFE_1_CLK>,
                     <&camcc CAM_CC_CPAS_IFE_2_CLK>,
                     <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
                     <&camcc CAM_CC_CSID_CLK>,
                     <&camcc CAM_CC_CSIPHY0_CLK>,
                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY1_CLK>,
                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY2_CLK>,
                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY3_CLK>,
                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY4_CLK>,
                     <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY5_CLK>,
                     <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
                     <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
                     <&camcc CAM_CC_IFE_0_CLK>,
                     <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
                     <&camcc CAM_CC_IFE_1_CLK>,
                     <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
                     <&camcc CAM_CC_IFE_2_CLK>,
                     <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CLK>,
                     <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
            clock-names = "camnoc_axi",
                          "cpas_ahb",
                          "cpas_fast_ahb",
                          "cpas_vfe0",
                          "cpas_vfe1",
                          "cpas_vfe2",
                          "cpas_vfe_lite",
                          "csid",
                          "csiphy0",
                          "csiphy0_timer",
                          "csiphy1",
                          "csiphy1_timer",
                          "csiphy2",
                          "csiphy2_timer",
                          "csiphy3",
                          "csiphy3_timer",
                          "csiphy4",
                          "csiphy4_timer",
                          "csiphy5",
                          "csiphy5_timer",
                          "csiphy_rx",
                          "gcc_axi_hf",
                          "qdss_debug_xo",
                          "vfe0",
                          "vfe0_fast_ahb",
                          "vfe1",
                          "vfe1_fast_ahb",
                          "vfe2",
                          "vfe2_fast_ahb",
                          "vfe_lite",
                          "vfe_lite_ahb",
                          "vfe_lite_cphy_rx",
                          "vfe_lite_csid";
            interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
            interrupt-names = "csid0",
                              "csid1",
                              "csid2",
                              "csid_lite0",
                              "csid_lite1",
                              "csiphy0",
                              "csiphy1",
                              "csiphy2",
                              "csiphy3",
                              "csiphy4",
                              "csiphy5",
                              "vfe0",
                              "vfe1",
                              "vfe2",
                              "vfe_lite0",
                              "vfe_lite1";
            interconnects = <&gem_noc MASTER_APPSS_PROC 0
                             &config_noc SLAVE_CAMERA_CFG 0>,
                            <&mmss_noc MASTER_CAMNOC_HF 0
                             &mc_virt SLAVE_EBI1 0>;
            interconnect-names = "ahb", "hf_mnoc";
            iommus = <&apps_smmu 0x800 0x20>,
                     <&apps_smmu 0x18a0 0x40>,
                     <&apps_smmu 0x1860 0x00>;
            power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
                            <&camcc CAM_CC_IFE_1_GDSC>,
                            <&camcc CAM_CC_IFE_2_GDSC>,
                            <&camcc CAM_CC_TITAN_TOP_GDSC>;
            power-domain-names = "ife0", "ife1", "ife2", "top";
            vdd-csiphy01-0p9-supply = <&vreg_0p9>;
            vdd-csiphy01-1p2-supply = <&vreg_1p2>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@1 {
                    reg = <1>;

                    csiphy1_ep: endpoint {
                        data-lanes = <0 1>;
                        remote-endpoint = <&camera_sensor>;
                    };
                };
            };
        };
    };
