# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/aspeed,ast2600-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED PCIe Root Complex Controller

maintainers:
  - Jacky Chou <jacky_chou@aspeedtech.com>

description:
  The ASPEED PCIe Root Complex controller provides PCI Express Root Complex
  functionality for ASPEED SoCs, such as the AST2600 and AST2700.
  This controller enables connectivity to PCIe endpoint devices, supporting
  memory and I/O windows, MSI and INTx interrupts, and integration with
  the SoC's clock, reset, and pinctrl subsystems. On AST2600, the PCIe Root
  Port device number is always 8.

properties:
  compatible:
    enum:
      - aspeed,ast2600-pcie
      - aspeed,ast2700-pcie

  reg:
    maxItems: 1

  ranges:
    minItems: 2
    maxItems: 2

  interrupts:
    maxItems: 1
    description: INTx and MSI interrupt

  resets:
    items:
      - description: PCIe controller reset

  reset-names:
    items:
      - const: h2x

  aspeed,ahbc:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the ASPEED AHB Controller (AHBC) syscon node.
      This reference is used by the PCIe controller to access
      system-level configuration registers related to the AHB bus.
      To enable AHB access for the PCIe controller.

  aspeed,pciecfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the ASPEED PCIe configuration syscon node.
      This reference allows the PCIe controller to access
      SoC-specific PCIe configuration registers. There are the others
      functions such PCIe RC and PCIe EP will use this common register
      to configure the SoC interfaces.

  interrupt-controller: true

patternProperties:
  "^pcie@[0-9a-f]+,0$":
    type: object
    $ref: /schemas/pci/pci-pci-bridge.yaml#

    properties:
      reg:
        maxItems: 1

      resets:
        items:
          - description: PERST# signal

      reset-names:
        items:
          - const: perst

      clocks:
        maxItems: 1

      phys:
        maxItems: 1

    required:
      - resets
      - reset-names
      - clocks
      - phys
      - ranges

    unevaluatedProperties: false

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: aspeed,ast2600-pcie
    then:
      required:
        - aspeed,ahbc
    else:
      properties:
        aspeed,ahbc: false
  - if:
      properties:
        compatible:
          contains:
            const: aspeed,ast2700-pcie
    then:
      required:
        - aspeed,pciecfg
    else:
      properties:
        aspeed,pciecfg: false

required:
  - reg
  - interrupts
  - bus-range
  - ranges
  - resets
  - reset-names
  - msi-controller
  - interrupt-controller
  - interrupt-map-mask
  - interrupt-map

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/ast2600-clock.h>

    pcie0: pcie@1e770000 {
      compatible = "aspeed,ast2600-pcie";
      device_type = "pci";
      reg = <0x1e770000 0x100>;
      #address-cells = <3>;
      #size-cells = <2>;
      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
      bus-range = <0x00 0xff>;

      ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
                0x02000000 0x0 0x60000000 0x60000000 0x0 0x20000000>;

      resets = <&syscon ASPEED_RESET_H2X>;
      reset-names = "h2x";

      #interrupt-cells = <1>;
      msi-controller;

      aspeed,ahbc = <&ahbc>;

      interrupt-controller;
      interrupt-map-mask = <0 0 0 7>;
      interrupt-map = <0 0 0 1 &pcie0 0>,
                      <0 0 0 2 &pcie0 1>,
                      <0 0 0 3 &pcie0 2>,
                      <0 0 0 4 &pcie0 3>;

      pcie@8,0 {
        compatible = "pciclass,0604";
        reg = <0x00004000 0 0 0 0>;
        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
        reset-names = "perst";
        clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcierc1_default>;
        phys = <&pcie_phy1>;
        ranges;
      };
    };
