# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PCIe controller on MediaTek SoCs

maintainers:
  - Christian Marangi <ansuelsmth@gmail.com>

properties:
  compatible:
    enum:
      - mediatek,mt2701-pcie
      - mediatek,mt7623-pcie

  reg:
    minItems: 4
    maxItems: 4

  reg-names:
    items:
      - const: subsys
      - const: port0
      - const: port1
      - const: port2

  clocks:
    minItems: 4
    maxItems: 4

  clock-names:
    items:
      - const: free_ck
      - const: sys_ck0
      - const: sys_ck1
      - const: sys_ck2

  resets:
    minItems: 3
    maxItems: 3

  reset-names:
    items:
      - const: pcie-rst0
      - const: pcie-rst1
      - const: pcie-rst2

  phys:
    minItems: 3
    maxItems: 3

  phy-names:
    items:
      - const: pcie-phy0
      - const: pcie-phy1
      - const: pcie-phy2

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - ranges
  - clocks
  - clock-names
  - '#interrupt-cells'
  - resets
  - reset-names
  - phys
  - phy-names
  - power-domains
  - pcie@0,0
  - pcie@1,0
  - pcie@2,0

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#

unevaluatedProperties: false

examples:
  # MT7623
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/mt2701-clk.h>
    #include <dt-bindings/reset/mt2701-resets.h>
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/power/mt2701-power.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie@1a140000 {
            compatible = "mediatek,mt7623-pcie";
            device_type = "pci";
            reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
                  <0 0x1a142000 0 0x1000>, /* Port0 registers */
                  <0 0x1a143000 0 0x1000>, /* Port1 registers */
                  <0 0x1a144000 0 0x1000>; /* Port2 registers */
            reg-names = "subsys", "port0", "port1", "port2";
            #address-cells = <3>;
            #size-cells = <2>;
            #interrupt-cells = <1>;
            interrupt-map-mask = <0xf800 0 0 0>;
            interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
                            <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
                            <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
            clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
                    <&hifsys CLK_HIFSYS_PCIE0>,
                    <&hifsys CLK_HIFSYS_PCIE1>,
                    <&hifsys CLK_HIFSYS_PCIE2>;
            clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
            resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
                     <&hifsys MT2701_HIFSYS_PCIE1_RST>,
                     <&hifsys MT2701_HIFSYS_PCIE2_RST>;
            reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
            phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
                   <&pcie2_phy PHY_TYPE_PCIE>;
            phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
            power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
            bus-range = <0x00 0xff>;
            ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>,	/* I/O space */
                     <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;	/* memory space */

            pcie@0,0 {
                device_type = "pci";
                reg = <0x0000 0 0 0 0>;
                #address-cells = <3>;
                #size-cells = <2>;
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 0 0>;
                interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
                ranges;
            };

            pcie@1,0 {
                device_type = "pci";
                reg = <0x0800 0 0 0 0>;
                #address-cells = <3>;
                #size-cells = <2>;
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 0 0>;
                interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
                ranges;
            };

            pcie@2,0 {
                device_type = "pci";
                reg = <0x1000 0 0 0 0>;
                #address-cells = <3>;
                #size-cells = <2>;
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 0 0>;
                interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
                ranges;
            };
        };
    };
