# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq5018.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IPQ5018 PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <mani@kernel.org>

properties:
  compatible:
    enum:
      - qcom,pcie-ipq5018

  reg:
    minItems: 5
    maxItems: 6

  reg-names:
    minItems: 5
    items:
      - const: dbi
      - const: elbi
      - const: atu
      - const: parf
      - const: config
      - const: mhi

  clocks:
    maxItems: 6

  clock-names:
    items:
      - const: iface # PCIe to SysNOC BIU clock
      - const: axi_m # AXI Master clock
      - const: axi_s # AXI Slave clock
      - const: ahb
      - const: aux
      - const: axi_bridge

  interrupts:
    maxItems: 9

  interrupt-names:
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7
      - const: global

  resets:
    maxItems: 8

  reset-names:
    items:
      - const: pipe
      - const: sleep
      - const: sticky # Core sticky reset
      - const: axi_m # AXI master reset
      - const: axi_s # AXI slave reset
      - const: ahb
      - const: axi_m_sticky # AXI master sticky reset
      - const: axi_s_sticky # AXI slave sticky reset

required:
  - resets
  - reset-names

allOf:
  - $ref: qcom,pcie-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/reset/qcom,gcc-ipq5018.h>

    pcie@a0000000 {
        compatible = "qcom,pcie-ipq5018";
        reg = <0xa0000000 0xf1d>,
              <0xa0000f20 0xa8>,
              <0xa0001000 0x1000>,
              <0x00080000 0x3000>,
              <0xa0100000 0x1000>,
              <0x00083000 0x1000>;
        reg-names = "dbi",
                    "elbi",
                    "atu",
                    "parf",
                    "config",
                    "mhi";
        ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
                 <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;

        device_type = "pci";
        linux,pci-domain = <0>;
        bus-range = <0x00 0xff>;
        num-lanes = <2>;
        #address-cells = <3>;
        #size-cells = <2>;

        /* The controller supports Gen3, but the connected PHY is Gen2-capable */
        max-link-speed = <2>;

        clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
                 <&gcc GCC_PCIE0_AXI_M_CLK>,
                 <&gcc GCC_PCIE0_AXI_S_CLK>,
                 <&gcc GCC_PCIE0_AHB_CLK>,
                 <&gcc GCC_PCIE0_AUX_CLK>,
                 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
        clock-names = "iface",
                      "axi_m",
                      "axi_s",
                      "ahb",
                      "aux",
                      "axi_bridge";

        msi-map = <0x0 &v2m0 0x0 0xff8>;

        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "msi0",
                          "msi1",
                          "msi2",
                          "msi3",
                          "msi4",
                          "msi5",
                          "msi6",
                          "msi7",
                          "global";

        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 0x7>;
        interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

        phys = <&pcie0_phy>;
        phy-names = "pciephy";

        resets = <&gcc GCC_PCIE0_PIPE_ARES>,
                 <&gcc GCC_PCIE0_SLEEP_ARES>,
                 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
                 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
                 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
                 <&gcc GCC_PCIE0_AHB_ARES>,
                 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
                 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
        reset-names = "pipe",
                      "sleep",
                      "sticky",
                      "axi_m",
                      "axi_s",
                      "ahb",
                      "axi_m_sticky",
                      "axi_s_sticky";

        perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
        wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;

        pcie@0 {
            device_type = "pci";
            reg = <0x0 0x0 0x0 0x0 0x0>;
            bus-range = <0x01 0xff>;

            #address-cells = <3>;
            #size-cells = <2>;
            ranges;
        };
    };
