# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq6018.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IPQ6018 PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <mani@kernel.org>

properties:
  compatible:
    enum:
      - qcom,pcie-ipq6018
      - qcom,pcie-ipq8074-gen3

  reg:
    minItems: 5
    maxItems: 6

  reg-names:
    minItems: 5
    items:
      - const: dbi
      - const: elbi
      - const: atu
      - const: parf
      - const: config
      - const: mhi

  clocks:
    maxItems: 5

  clock-names:
    items:
      - const: iface # PCIe to SysNOC BIU clock
      - const: axi_m # AXI Master clock
      - const: axi_s # AXI Slave clock
      - const: axi_bridge
      - const: rchng

  interrupts:
    maxItems: 9

  interrupt-names:
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7
      - const: global

  resets:
    maxItems: 8

  reset-names:
    items:
      - const: pipe
      - const: sleep
      - const: sticky # Core sticky reset
      - const: axi_m # AXI master reset
      - const: axi_s # AXI slave reset
      - const: ahb
      - const: axi_m_sticky # AXI master sticky reset
      - const: axi_s_sticky # AXI slave sticky reset

required:
  - resets
  - reset-names

allOf:
  - $ref: qcom,pcie-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/reset/qcom,gcc-ipq6018.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie@20000000 {
            compatible = "qcom,pcie-ipq6018";
            reg = <0x0 0x20000000 0x0 0xf1d>,
                  <0x0 0x20000f20 0x0 0xa8>,
                  <0x0 0x20001000 0x0 0x1000>,
                  <0x0 0x80000 0x0 0x4000>,
                  <0x0 0x20100000 0x0 0x1000>;
            reg-names = "dbi", "elbi", "atu", "parf", "config";
            ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
                     <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;

            device_type = "pci";
            linux,pci-domain = <0>;
            bus-range = <0x00 0xff>;
            num-lanes = <1>;
            max-link-speed = <3>;
            #address-cells = <3>;
            #size-cells = <2>;

            clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
                     <&gcc GCC_PCIE0_AXI_M_CLK>,
                     <&gcc GCC_PCIE0_AXI_S_CLK>,
                     <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
                     <&gcc PCIE0_RCHNG_CLK>;
            clock-names = "iface",
                          "axi_m",
                          "axi_s",
                          "axi_bridge",
                          "rchng";

            interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "msi0",
                              "msi1",
                              "msi2",
                              "msi3",
                              "msi4",
                              "msi5",
                              "msi6",
                              "msi7",
                              "global";

            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0x7>;
            interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
                            <0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
                            <0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
                            <0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

            phys = <&pcie_phy>;
            phy-names = "pciephy";

            resets = <&gcc GCC_PCIE0_PIPE_ARES>,
                     <&gcc GCC_PCIE0_SLEEP_ARES>,
                     <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
                     <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
                     <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
                     <&gcc GCC_PCIE0_AHB_ARES>,
                     <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
                     <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
            reset-names = "pipe",
                          "sleep",
                          "sticky",
                          "axi_m",
                          "axi_s",
                          "ahb",
                          "axi_m_sticky",
                          "axi_s_sticky";

            pcie@0 {
                device_type = "pci";
                reg = <0x0 0x0 0x0 0x0 0x0>;
                bus-range = <0x01 0xff>;

                #address-cells = <3>;
                #size-cells = <2>;
                ranges;
            };
        };
    };
