# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip MIPI D-/C-PHY with Samsung IP block

maintainers:
  - Guochun Huang <hero.huang@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,rk3576-mipi-dcphy
      - rockchip,rk3588-mipi-dcphy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 1
    description: |
      Argument is mode to operate in. Supported modes are:
        - PHY_TYPE_DPHY
        - PHY_TYPE_CPHY
      See include/dt-bindings/phy/phy.h for constants.

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: pclk
      - const: ref

  resets:
    maxItems: 4

  reset-names:
    items:
      - const: m_phy
      - const: apb
      - const: grf
      - const: s_phy

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the 'mipi dcphy general register files'.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
    #include <dt-bindings/reset/rockchip,rk3588-cru.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      phy@feda0000 {
        compatible = "rockchip,rk3588-mipi-dcphy";
        reg = <0x0 0xfeda0000 0x0 0x10000>;
        clocks = <&cru PCLK_MIPI_DCPHY0>,
                 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
        clock-names = "pclk", "ref";
        resets = <&cru SRST_M_MIPI_DCPHY0>,
                 <&cru SRST_P_MIPI_DCPHY0>,
                 <&cru SRST_P_MIPI_DCPHY0_GRF>,
                 <&cru SRST_S_MIPI_DCPHY0>;
        reset-names = "m_phy", "apb", "grf", "s_phy";
        rockchip,grf = <&mipidcphy0_grf>;
        #phy-cells = <1>;
      };
    };
