# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mediatek,mt8173-afe-pcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek AFE PCM controller for MT8173

maintainers:
  - Trevor Wu <trevor.wu@mediatek.com>

properties:
  compatible:
    const: mediatek,mt8173-afe-pcm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: audio infra sys clock
      - description: audio top mux
      - description: audio intbus mux
      - description: apll1 clock
      - description: apll2 clock
      - description: i2s0 mclk mux
      - description: i2s1 mclk mux
      - description: i2s2 mclk mux
      - description: i2s3 mclk mux
      - description: i2s3 bclk mux

  clock-names:
    items:
      - const: infra_sys_audio_clk
      - const: top_pdn_audio
      - const: top_pdn_aud_intbus
      - const: bck0
      - const: bck1
      - const: i2s0_m
      - const: i2s1_m
      - const: i2s2_m
      - const: i2s3_m
      - const: i2s3_b

  power-domains:
    maxItems: 1

  memory-region:
    description: memory region for audio DMA buffers
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/mt8173-power.h>

    mt8173-afe-pcm@11220000 {
        compatible = "mediatek,mt8173-afe-pcm";
        reg = <0x11220000 0x1000>;
        interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
        power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
        clocks = <&infracfg CLK_INFRA_AUDIO>,
                 <&topckgen CLK_TOP_AUDIO_SEL>,
                 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
                 <&topckgen CLK_TOP_APLL1_DIV0>,
                 <&topckgen CLK_TOP_APLL2_DIV0>,
                 <&topckgen CLK_TOP_I2S0_M_SEL>,
                 <&topckgen CLK_TOP_I2S1_M_SEL>,
                 <&topckgen CLK_TOP_I2S2_M_SEL>,
                 <&topckgen CLK_TOP_I2S3_M_SEL>,
                 <&topckgen CLK_TOP_I2S3_B_SEL>;
         clock-names = "infra_sys_audio_clk",
                       "top_pdn_audio",
                       "top_pdn_aud_intbus",
                       "bck0",
                       "bck1",
                       "i2s0_m",
                       "i2s1_m",
                       "i2s2_m",
                       "i2s3_m",
                       "i2s3_b";
          memory-region = <&afe_dma_mem>;
    };
