# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mediatek,mt8189-afe-pcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Audio Front End PCM controller for MT8189

maintainers:
  - Darren Ye <darren.ye@mediatek.com>
  - Cyril Chao <cyril.chao@mediatek.com>

properties:
  compatible:
    const: mediatek,mt8189-afe-pcm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  memory-region:
    maxItems: 1

  mediatek,apmixedsys:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: To set up the apll12 tuner

  power-domains:
    maxItems: 1

  clocks:
    items:
      - description: mux for audio intbus
      - description: mux for audio engen1
      - description: mux for audio engen2
      - description: mux for audio h
      - description: audio apll1 clock
      - description: audio apll2 clock
      - description: audio apll1 divide4
      - description: audio apll2 divide4
      - description: audio apll12 divide for i2sin0
      - description: audio apll12 divide for i2sin1
      - description: audio apll12 divide for i2sout0
      - description: audio apll12 divide for i2sout1
      - description: audio apll12 divide for fmi2s
      - description: audio apll12 divide for tdmout mck
      - description: audio apll12 divide for tdmout bck
      - description: mux for audio apll1
      - description: mux for audio apll2
      - description: mux for i2sin0 mck
      - description: mux for i2sin1 mck
      - description: mux for i2sout0 mck
      - description: mux for i2sout1 mck
      - description: mux for fmi2s mck
      - description: mux for tdmout mck
      - description: 26m clock
      - description: audio slv clock
      - description: audio mst clock
      - description: audio intbus clock

  clock-names:
    items:
      - const: top_aud_intbus
      - const: top_aud_eng1
      - const: top_aud_eng2
      - const: top_aud_h
      - const: apll1
      - const: apll2
      - const: apll1_d4
      - const: apll2_d4
      - const: apll12_div_i2sin0
      - const: apll12_div_i2sin1
      - const: apll12_div_i2sout0
      - const: apll12_div_i2sout1
      - const: apll12_div_fmi2s
      - const: apll12_div_tdmout_m
      - const: apll12_div_tdmout_b
      - const: top_apll1
      - const: top_apll2
      - const: top_i2sin0
      - const: top_i2sin1
      - const: top_i2sout0
      - const: top_i2sout1
      - const: top_fmi2s
      - const: top_dptx
      - const: clk26m
      - const: aud_slv_ck_peri
      - const: aud_mst_ck_peri
      - const: aud_intbus_ck_peri

required:
  - compatible
  - reg
  - interrupts
  - memory-region
  - power-domains
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        afe@11050000 {
            compatible = "mediatek,mt8189-afe-pcm";
            reg = <0 0x11050000 0 0x10000>;
            interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
            memory-region = <&afe_dma_mem_reserved>;
            pinctrl-names = "default";
            pinctrl-0 = <&aud_pins_default>;
            power-domains = <&scpsys 1>; //MT8189_POWER_DOMAIN_AUDIO
            clocks = <&topckgen_clk 23>, //CLK_TOP_AUD_INTBUS_SEL
                     <&topckgen_clk 39>, //CLK_TOP_AUD_ENGEN1_SEL
                     <&topckgen_clk 40>, //CLK_TOP_AUD_ENGEN2_SEL
                     <&topckgen_clk 49>, //CLK_TOP_AUDIO_H_SEL
                     <&topckgen_clk 146>, //CLK_TOP_APLL1
                     <&topckgen_clk 151>, //CLK_TOP_APLL2
                     <&topckgen_clk 148>, //CLK_TOP_APLL1_D4
                     <&topckgen_clk 153>, //CLK_TOP_APLL2_D4
                     <&topckgen_clk 93>, //CLK_TOP_APLL12_CK_DIV_I2SIN0
                     <&topckgen_clk 94>, //CLK_TOP_APLL12_CK_DIV_I2SIN1
                     <&topckgen_clk 95>, //CLK_TOP_APLL12_CK_DIV_I2SOUT0
                     <&topckgen_clk 96>, //CLK_TOP_APLL12_CK_DIV_I2SOUT1
                     <&topckgen_clk 97>, //CLK_TOP_APLL12_CK_DIV_FMI2S
                     <&topckgen_clk 98>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M
                     <&topckgen_clk 99>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_B
                     <&topckgen_clk 44>, //CLK_TOP_AUD_1_SEL
                     <&topckgen_clk 45>, //CLK_TOP_AUD_2_SEL
                     <&topckgen_clk 78>, //CLK_TOP_APLL_I2SIN0_MCK_SEL
                     <&topckgen_clk 79>, //CLK_TOP_APLL_I2SIN1_MCK_SEL
                     <&topckgen_clk 84>, //CLK_TOP_APLL_I2SOUT0_MCK_SEL
                     <&topckgen_clk 85>, //CLK_TOP_APLL_I2SOUT1_MCK_SEL
                     <&topckgen_clk 90>, //CLK_TOP_APLL_FMI2S_MCK_SEL
                     <&topckgen_clk 91>, //CLK_TOP_APLL_TDMOUT_MCK_SEL
                     <&topckgen_clk 191>, //CLK_TOP_TCK_26M_MX9
                     <&pericfg_ao_clk 77>, //CLK_PERAO_AUDIO0
                     <&pericfg_ao_clk 78>, //CLK_PERAO_AUDIO1
                     <&pericfg_ao_clk 79>; //CLK_PERAO_AUDIO2
            clock-names = "top_aud_intbus",
                          "top_aud_eng1",
                          "top_aud_eng2",
                          "top_aud_h",
                          "apll1",
                          "apll2",
                          "apll1_d4",
                          "apll2_d4",
                          "apll12_div_i2sin0",
                          "apll12_div_i2sin1",
                          "apll12_div_i2sout0",
                          "apll12_div_i2sout1",
                          "apll12_div_fmi2s",
                          "apll12_div_tdmout_m",
                          "apll12_div_tdmout_b",
                          "top_apll1",
                          "top_apll2",
                          "top_i2sin0",
                          "top_i2sin1",
                          "top_i2sout0",
                          "top_i2sout1",
                          "top_fmi2s",
                          "top_dptx",
                          "clk26m",
                          "aud_slv_ck_peri",
                          "aud_mst_ck_peri",
                          "aud_intbus_ck_peri";
        };
    };

...
