# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nuvoton,npcm-pspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton NPCM Peripheral SPI (PSPI) Controller

maintainers:
  - Tomer Maimon <tmaimon77@gmail.com>

allOf:
  - $ref: spi-controller.yaml#

description:
  Nuvoton NPCM Peripheral Serial Peripheral Interface (PSPI) controller.
  Nuvoton NPCM7xx SOC supports two PSPI channels.
  Nuvoton NPCM8xx SOC support one PSPI channel.

properties:
  compatible:
    enum:
      - nuvoton,npcm750-pspi # Poleg NPCM7XX
      - nuvoton,npcm845-pspi # Arbel NPCM8XX

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description: PSPI reference clock.

  clock-names:
    items:
      - const: clk_apb5

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
    #include "dt-bindings/gpio/gpio.h"
    spi0: spi@f0200000 {
        compatible = "nuvoton,npcm750-pspi";
        reg = <0xf0200000 0x1000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pspi1_pins>;
        #address-cells = <1>;
        #size-cells = <0>;
        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk NPCM7XX_CLK_APB5>;
        clock-names = "clk_apb5";
        resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
        cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
    };

