# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spmi/qcom,glymur-spmi-pmic-arb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Glymur SPMI Controller (PMIC Arbiter v8)

maintainers:
  - David Collins <david.collins@oss.qualcomm.com>

description: |
  The Glymur SPMI PMIC Arbiter implements HW version 8 and it's an SPMI
  controller with wrapping arbitration logic to allow for multiple on-chip
  devices to control up to 4 SPMI separate buses.

  The PMIC Arbiter can also act as an interrupt controller, providing interrupts
  to slave devices.

allOf:
  - $ref: /schemas/spmi/qcom,spmi-pmic-arb-common.yaml

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,kaanapali-spmi-pmic-arb
          - const: qcom,glymur-spmi-pmic-arb
      - enum:
          - qcom,glymur-spmi-pmic-arb

  reg:
    items:
      - description: core registers
      - description: tx-channel per virtual slave registers
      - description: rx-channel (called observer) per virtual slave registers
      - description: channel to PMIC peripheral mapping registers

  reg-names:
    items:
      - const: core
      - const: chnls
      - const: obsrvr
      - const: chnl_map

  ranges: true

  '#address-cells':
    const: 2

  '#size-cells':
    const: 2

patternProperties:
  "^spmi@[a-f0-9]+$":
    type: object
    $ref: /schemas/spmi/spmi.yaml
    unevaluatedProperties: false

    properties:
      reg:
        items:
          - description: configuration registers
          - description: interrupt controller registers
          - description: channel owner EE mapping registers

      reg-names:
        items:
          - const: cnfg
          - const: intr
          - const: chnl_owner

      interrupts:
        maxItems: 1

      interrupt-names:
        const: periph_irq

      interrupt-controller: true

      '#interrupt-cells':
        const: 4
        description: |
          cell 1: slave ID for the requested interrupt (0-15)
          cell 2: peripheral ID for requested interrupt (0-255)
          cell 3: the requested peripheral interrupt (0-7)
          cell 4: interrupt flags indicating level-sense information,
                  as defined in dt-bindings/interrupt-controller/irq.h

required:
  - compatible
  - reg-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        arbiter@c400000 {
            compatible = "qcom,glymur-spmi-pmic-arb";
            reg = <0x0 0xc400000 0x0 0x3000>,
                  <0x0 0xc900000 0x0 0x400000>,
                  <0x0 0xc4c0000 0x0 0x400000>,
                  <0x0 0xc403000 0x0 0x8000>;
            reg-names = "core", "chnls", "obsrvr", "chnl_map";

            qcom,ee = <0>;
            qcom,channel = <0>;

            #address-cells = <2>;
            #size-cells = <2>;
            ranges;

            spmi@c426000 {
                reg = <0x0 0xc426000 0x0 0x4000>,
                      <0x0 0xc8c0000 0x0 0x10000>,
                      <0x0 0xc42a000 0x0 0x8000>;
                reg-names = "cnfg", "intr", "chnl_owner";

                interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "periph_irq";
                interrupt-controller;
                #interrupt-cells = <4>;

                #address-cells = <2>;
                #size-cells = <0>;
            };

            spmi@c437000 {
                reg = <0x0 0xc437000 0x0 0x4000>,
                      <0x0 0xc8d0000 0x0 0x10000>,
                      <0x0 0xc43b000 0x0 0x8000>;
                reg-names = "cnfg", "intr", "chnl_owner";

                interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "periph_irq";
                interrupt-controller;
                #interrupt-cells = <4>;

                #address-cells = <2>;
                #size-cells = <0>;
            };
        };
    };
