// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree file for the J722S MAIN domain peripherals
 *
 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>

/ {
	serdes_refclk: clk-0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
};

&cbass_main {
	serdes_wiz0: phy@f000000 {
		compatible = "ti,am64-wiz-10g";
		ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		num-lanes = <1>;
		#reset-cells = <1>;
		#clock-cells = <1>;

		assigned-clocks = <&k3_clks 279 1>;
		assigned-clock-parents = <&k3_clks 279 5>;

		status = "disabled";

		serdes0: serdes@f000000 {
			compatible = "ti,j721e-serdes-10g";
			reg = <0x0f000000 0x00010000>;
			reg-names = "torrent_phy";
			resets = <&serdes_wiz0 0>;
			reset-names = "torrent_reset";
			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
			clock-names = "refclk", "phy_en_refclk";
			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
			assigned-clock-parents = <&k3_clks 279 1>,
						 <&k3_clks 279 1>,
						 <&k3_clks 279 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
		};
	};

	serdes_wiz1: phy@f010000 {
		compatible = "ti,am64-wiz-10g";
		ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		num-lanes = <1>;
		#reset-cells = <1>;
		#clock-cells = <1>;

		assigned-clocks = <&k3_clks 280 1>;
		assigned-clock-parents = <&k3_clks 280 5>;

		status = "disabled";

		serdes1: serdes@f010000 {
			compatible = "ti,j721e-serdes-10g";
			reg = <0x0f010000 0x00010000>;
			reg-names = "torrent_phy";
			resets = <&serdes_wiz1 0>;
			reset-names = "torrent_reset";
			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
			clock-names = "refclk", "phy_en_refclk";
			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
			assigned-clock-parents = <&k3_clks 280 1>,
						 <&k3_clks 280 1>,
						 <&k3_clks 280 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
		};
	};

	pcie0_rc: pcie@f102000 {
		compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
		reg = <0x00 0x0f102000 0x00 0x1000>,
		      <0x00 0x0f100000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
			 <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		max-link-speed = <3>;
		num-lanes = <1>;
		power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
		clock-names = "fck", "pcie_refclk";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb010>;
		cdns,no-bar-match-nbits = <64>;
		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
		status = "disabled";
	};

	usbss1: usb@f920000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x0f920000 0x00 0x100>;
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		usb1: usb@31200000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x31200000 0x00 0x10000>,
			      <0x00 0x31210000 0x00 0x10000>,
			      <0x00 0x31220000 0x00 0x10000>;
			reg-names = "otg",
				    "xhci",
				    "dev";
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	ti_csi2rx1: ticsi2rx@30122000 {
		compatible = "ti,j721e-csi2rx-shim";
		reg = <0x00 0x30122000 0x00 0x1000>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		dmas = <&main_bcdma_csi 0 0x5100 0>;
		dma-names = "rx0";
		power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";

		cdns_csi2rx1: csi-bridge@30121000 {
			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
			reg = <0x00 0x30121000 0x00 0x1000>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error_irq", "irq";
			clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>,
				 <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				      "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy1>;
			phy-names = "dphy";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi1_port0: port@0 {
					reg = <0>;
					status = "disabled";
				};

				csi1_port1: port@1 {
					reg = <1>;
					status = "disabled";
				};

				csi1_port2: port@2 {
					reg = <2>;
					status = "disabled";
				};

				csi1_port3: port@3 {
					reg = <3>;
					status = "disabled";
				};

				csi1_port4: port@4 {
					reg = <4>;
					status = "disabled";
				};
			};
		};
	};

	ti_csi2rx2: ticsi2rx@30142000 {
		compatible = "ti,j721e-csi2rx-shim";
		reg = <0x00 0x30142000 0x00 0x1000>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
		dmas = <&main_bcdma_csi 0 0x5200 0>;
		dma-names = "rx0";
		status = "disabled";

		cdns_csi2rx2: csi-bridge@30141000 {
			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
			reg = <0x00 0x30141000 0x00 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error_irq", "irq";
			clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>,
				 <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				      "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy2>;
			phy-names = "dphy";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi2_port0: port@0 {
					reg = <0>;
					status = "disabled";
				};

				csi2_port1: port@1 {
					reg = <1>;
					status = "disabled";
				};

				csi2_port2: port@2 {
					reg = <2>;
					status = "disabled";
				};

				csi2_port3: port@3 {
					reg = <3>;
					status = "disabled";
				};

				csi2_port4: port@4 {
					reg = <4>;
					status = "disabled";
				};
			};
		};
	};

	ti_csi2rx3: ticsi2rx@30162000 {
		compatible = "ti,j721e-csi2rx-shim";
		reg = <0x00 0x30162000 0x00 0x1000>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		dmas = <&main_bcdma_csi 0 0x5300 0>;
		dma-names = "rx0";
		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";

		cdns_csi2rx3: csi-bridge@30161000 {
			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
			reg = <0x00 0x30161000 0x00 0x1000>;
			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error_irq", "irq";
			clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>,
				 <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				      "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy3>;
			phy-names = "dphy";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi3_port0: port@0 {
					reg = <0>;
					status = "disabled";
				};

				csi3_port1: port@1 {
					reg = <1>;
					status = "disabled";
				};

				csi3_port2: port@2 {
					reg = <2>;
					status = "disabled";
				};

				csi3_port3: port@3 {
					reg = <3>;
					status = "disabled";
				};

				csi3_port4: port@4 {
					reg = <4>;
					status = "disabled";
				};
			};
		};
	};

	dphy1: phy@30130000 {
		compatible = "cdns,dphy-rx";
		reg = <0x00 0x30130000 0x00 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	dphy2: phy@30150000 {
		compatible = "cdns,dphy-rx";
		reg = <0x00 0x30150000 0x00 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	dphy3: phy@30170000 {
		compatible = "cdns,dphy-rx";
		reg = <0x00 0x30170000 0x00 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_r5fss0: r5fss@78400000 {
		compatible = "ti,am62-r5fss";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x78400000 0x00 0x78400000 0x8000>,
			 <0x78500000 0x00 0x78500000 0x8000>;
		power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";

		main_r5fss0_core0: r5f@78400000 {
			compatible = "ti,am62-r5f";
			reg = <0x78400000 0x00008000>,
			      <0x78500000 0x00008000>;
			reg-names = "atcm", "btcm";
			resets = <&k3_reset 262 1>;
			firmware-name = "j722s-main-r5f0_0-fw";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <262>;
			ti,sci-proc-ids = <0x04 0xff>;
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
			status = "disabled";
		};
	};

	c7x_0: dsp@7e000000 {
		compatible = "ti,am62a-c7xv-dsp";
		reg = <0x00 0x7e000000 0x00 0x00200000>;
		reg-names = "l2sram";
		resets = <&k3_reset 208 1>;
		firmware-name = "j722s-c71_0-fw";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <208>;
		ti,sci-proc-ids = <0x30 0xff>;
		status = "disabled";
	};

	c7x_1: dsp@7e200000 {
		compatible = "ti,am62a-c7xv-dsp";
		reg = <0x00 0x7e200000 0x00 0x00200000>;
		reg-names = "l2sram";
		resets = <&k3_reset 268 1>;
		firmware-name = "j722s-c71_1-fw";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <268>;
		ti,sci-proc-ids = <0x31 0xff>;
		status = "disabled";
	};

	e5010: jpeg-encoder@fd20000 {
		compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc";
		reg = <0x00 0xfd20000 0x00 0x100>,
		      <0x00 0xfd20200 0x00 0x200>;
		reg-names = "core", "mmu";
		clocks = <&k3_clks 201 0>;
		power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&main_bcdma_csi {
	compatible = "ti,j722s-dmss-bcdma-csi";
	reg = <0x00 0x4e230000 0x00 0x100>,
	      <0x00 0x4e180000 0x00 0x20000>,
	      <0x00 0x4e300000 0x00 0x10000>,
	      <0x00 0x4e100000 0x00 0x80000>;
	reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
	ti,sci-rm-range-tchan = <0x22>;
};

/* MCU domain overrides */

&mcu_r5fss0_core0 {
	firmware-name = "j722s-mcu-r5f0_0-fw";
};

/* Wakeup domain overrides */

&wkup_r5fss0_core0 {
	firmware-name = "j722s-wkup-r5f0_0-fw";
};

/* MAIN domain overrides */
&hsm {
	firmware-name = "j722s-hsm-m4f-fw";
};

&main_conf {
	serdes_ln_ctrl: mux-controller@4080 {
		compatible = "reg-mux";
		reg = <0x4080 0x14>;
		#mux-control-cells = <1>;
		mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
				<0x10 0x3>; /* SERDES1 lane0 select */
	};
};

&wkup_conf {
	pcie0_ctrl: pcie0-ctrl@4070 {
		compatible = "ti,j784s4-pcie-ctrl", "syscon";
		reg = <0x4070 0x4>;
	};
};

&oc_sram {
	reg = <0x00 0x70000000 0x00 0x40000>;
	ranges = <0x00 0x00 0x70000000 0x40000>;
};

&inta_main_dmss {
	ti,interrupt-ranges = <7 71 21>;
};

&main_gpio0 {
	gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
			<&main_pmx0 70 72 17>;
	ti,ngpio = <87>;
};

&main_gpio1 {
	gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
			<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
	gpio-reserved-ranges = <0 7>, <32 10>;
	ti,ngpio = <73>;
};