// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include / { interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; clocks { xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <38400000>; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; }; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a78c"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl0 MASTER_EPSS_L3_APPS &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a78c"; reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2_1>; power-domains = <&cpu_pd1>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; #cooling-cells = <2>; dynamic-power-coefficient = <472>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl0 MASTER_EPSS_L3_APPS &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_1: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a78c"; reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&l2_2>; power-domains = <&cpu_pd2>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; #cooling-cells = <2>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu2_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl0 MASTER_EPSS_L3_APPS &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a78c"; reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&l2_3>; power-domains = <&cpu_pd3>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; #cooling-cells = <2>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu2_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl0 MASTER_EPSS_L3_APPS &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu4: cpu@10000 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x10000>; enable-method = "psci"; next-level-cache = <&l2_4>; power-domains = <&cpu_pd4>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl1 MASTER_EPSS_L3_APPS &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_4: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_1>; }; }; cpu5: cpu@10100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x10100>; enable-method = "psci"; next-level-cache = <&l2_5>; power-domains = <&cpu_pd5>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl1 MASTER_EPSS_L3_APPS &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_5: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_1>; }; }; cpu6: cpu@10200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x10200>; enable-method = "psci"; next-level-cache = <&l2_6>; power-domains = <&cpu_pd6>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl1 MASTER_EPSS_L3_APPS &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_6: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_1>; }; }; cpu7: cpu@10300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x10300>; enable-method = "psci"; next-level-cache = <&l2_7>; power-domains = <&cpu_pd7>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl1 MASTER_EPSS_L3_APPS &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_7: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_1>; }; }; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; }; cluster1 { core0 { cpu = <&cpu4>; }; core1 { cpu = <&cpu5>; }; core2 { cpu = <&cpu6>; }; core3 { cpu = <&cpu7>; }; }; }; l3_0: l3-cache-0 { compatible = "cache"; cache-level = <3>; cache-unified; }; l3_1: l3-cache-1 { compatible = "cache"; cache-level = <3>; cache-unified; }; idle-states { entry-method = "psci"; little_cpu_sleep_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "silver-power-collapse"; arm,psci-suspend-param = <0x40000003>; entry-latency-us = <449>; exit-latency-us = <801>; min-residency-us = <1574>; local-timer-stop; }; little_cpu_sleep_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <602>; exit-latency-us = <961>; min-residency-us = <4288>; local-timer-stop; }; big_cpu_sleep_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "gold-power-collapse"; arm,psci-suspend-param = <0x40000003>; entry-latency-us = <549>; exit-latency-us = <901>; min-residency-us = <1774>; local-timer-stop; }; big_cpu_sleep_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <702>; exit-latency-us = <1061>; min-residency-us = <4488>; local-timer-stop; }; }; domain-idle-states { silver_cluster_sleep: cluster-sleep-0 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x41000044>; entry-latency-us = <2552>; exit-latency-us = <2848>; min-residency-us = <5908>; }; gold_cluster_sleep: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x41000044>; entry-latency-us = <2752>; exit-latency-us = <3048>; min-residency-us = <6118>; }; system_sleep: domain-sleep { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x42000144>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; }; }; }; cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-peak-kBps = <(681600 * 4) (921600 * 32)>; }; opp-1017600000 { opp-hz = /bits/ 64 <1017600000>; opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; }; opp-1267200000 { opp-hz = /bits/ 64 <1267200000>; opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; }; opp-1344000000 { opp-hz = /bits/ 64 <1344000000>; opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; }; opp-1420800000 { opp-hz = /bits/ 64 <1420800000>; opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; }; opp-1497600000 { opp-hz = /bits/ 64 <1497600000>; opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; }; opp-1574400000 { opp-hz = /bits/ 64 <1574400000>; opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; }; opp-1670400000 { opp-hz = /bits/ 64 <1670400000>; opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; }; opp-1747200000 { opp-hz = /bits/ 64 <1747200000>; opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; }; opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; }; opp-1977600000 { opp-hz = /bits/ 64 <1977600000>; opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; }; opp-2054400000 { opp-hz = /bits/ 64 <2054400000>; opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; }; opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; }; }; cpu2_opp_table: opp-table-cpu2 { compatible = "operating-points-v2"; opp-shared; opp-940800000 { opp-hz = /bits/ 64 <940800000>; opp-peak-kBps = <(681600 * 4) (921600 * 32)>; }; opp-1094400000 { opp-hz = /bits/ 64 <1094400000>; opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; }; opp-1267200000 { opp-hz = /bits/ 64 <1267200000>; opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; }; opp-1344000000 { opp-hz = /bits/ 64 <1344000000>; opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; }; opp-1420800000 { opp-hz = /bits/ 64 <1420800000>; opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; }; opp-1497600000 { opp-hz = /bits/ 64 <1497600000>; opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; }; opp-1574400000 { opp-hz = /bits/ 64 <1574400000>; opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; }; opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; }; opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; }; opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; }; opp-1977600000 { opp-hz = /bits/ 64 <1977600000>; opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; }; opp-2054400000 { opp-hz = /bits/ 64 <2054400000>; opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; }; opp-2131200000 { opp-hz = /bits/ 64 <2131200000>; opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; }; opp-2208000000 { opp-hz = /bits/ 64 <2208000000>; opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; }; opp-2284800000 { opp-hz = /bits/ 64 <2284800000>; opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; }; opp-2361600000 { opp-hz = /bits/ 64 <2361600000>; opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; }; }; cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; opp-844800000 { opp-hz = /bits/ 64 <844800000>; opp-peak-kBps = <(681600 * 4) (921600 * 32)>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; }; opp-1305600000 { opp-hz = /bits/ 64 <1305600000>; opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; }; opp-1382400000 { opp-hz = /bits/ 64 <1382400000>; opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; }; opp-1459200000 { opp-hz = /bits/ 64 <1459200000>; opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; }; opp-1497600000 { opp-hz = /bits/ 64 <1497600000>; opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; }; opp-1574400000 { opp-hz = /bits/ 64 <1574400000>; opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; }; opp-1651200000 { opp-hz = /bits/ 64 <1651200000>; opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; }; opp-1728000000 { opp-hz = /bits/ 64 <1728000000>; opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; }; opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; }; opp-1881600000 { opp-hz = /bits/ 64 <1881600000>; opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; }; opp-1958400000 { opp-hz = /bits/ 64 <1958400000>; opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; }; }; dummy_eud: dummy-sink { compatible = "arm,coresight-dummy-sink"; in-ports { port { eud_in: endpoint { remote-endpoint = <&swao_rep_out1>; }; }; }; }; firmware { scm: scm { compatible = "qcom,scm-qcs8300", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; }; }; memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0x0 0x80000000 0x0 0x0>; }; clk_virt: interconnect-0 { compatible = "qcom,qcs8300-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect-1 { compatible = "qcom,qcs8300-mc-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-120000000 { opp-hz = /bits/ 64 <120000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; }; pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = ; }; pmu-a78 { compatible = "arm,cortex-a78-pmu"; interrupts = ; }; psci { compatible = "arm,psci-1.0"; method = "smc"; cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; cluster_pd0: power-domain-cluster0 { #power-domain-cells = <0>; power-domains = <&system_pd>; domain-idle-states = <&gold_cluster_sleep>; }; cluster_pd1: power-domain-cluster1 { #power-domain-cells = <0>; power-domains = <&system_pd>; domain-idle-states = <&silver_cluster_sleep>; }; system_pd: power-domain-system { #power-domain-cells = <0>; domain-idle-states = <&system_sleep>; }; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; aop_image_mem: aop-image-region@90800000 { reg = <0x0 0x90800000 0x0 0x60000>; no-map; }; aop_cmd_db_mem: aop-cmd-db-region@90860000 { compatible = "qcom,cmd-db"; reg = <0x0 0x90860000 0x0 0x20000>; no-map; }; smem_mem: smem@90900000 { compatible = "qcom,smem"; reg = <0x0 0x90900000 0x0 0x200000>; no-map; hwlocks = <&tcsr_mutex 3>; }; gunyah_md_mem: gunyah-md-region@91a80000 { reg = <0x0 0x91a80000 0x0 0x80000>; no-map; }; lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { reg = <0x0 0x93b00000 0x0 0xf00000>; no-map; }; adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { reg = <0x0 0x94a00000 0x0 0x800000>; no-map; }; camera_mem: camera-region@95200000 { reg = <0x0 0x95200000 0x0 0x500000>; no-map; }; adsp_mem: adsp-region@95c00000 { no-map; reg = <0x0 0x95c00000 0x0 0x1e00000>; }; q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { reg = <0x0 0x97a00000 0x0 0x80000>; no-map; }; q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { reg = <0x0 0x97a80000 0x0 0x80000>; no-map; }; gpdsp_mem: gpdsp-region@97b00000 { reg = <0x0 0x97b00000 0x0 0x1e00000>; no-map; }; q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { reg = <0x0 0x99900000 0x0 0x80000>; no-map; }; cdsp_mem: cdsp-region@99980000 { reg = <0x0 0x99980000 0x0 0x1e00000>; no-map; }; gpu_microcode_mem: gpu-microcode-region@9b780000 { reg = <0x0 0x9b780000 0x0 0x2000>; no-map; }; cvp_mem: cvp-region@9b782000 { reg = <0x0 0x9b782000 0x0 0x700000>; no-map; }; video_mem: video-region@9be82000 { reg = <0x0 0x9be82000 0x0 0x700000>; no-map; }; }; smp2p-adsp { compatible = "qcom,smp2p"; interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; qcom,smem = <443>, <429>; qcom,local-pid = <0>; qcom,remote-pid = <2>; smp2p_adsp_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_adsp_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; }; smp2p-cdsp { compatible = "qcom,smp2p"; interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; qcom,smem = <94>, <432>; qcom,local-pid = <0>; qcom,remote-pid = <5>; smp2p_cdsp_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_cdsp_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; }; smp2p-gpdsp { compatible = "qcom,smp2p"; interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; qcom,smem = <617>, <616>; qcom,local-pid = <0>; qcom,remote-pid = <17>; smp2p_gpdsp_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_gpdsp_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; }; soc: soc@0 { compatible = "simple-bus"; ranges = <0 0 0 0 0x10 0>; #address-cells = <2>; #size-cells = <2>; gcc: clock-controller@100000 { compatible = "qcom,qcs8300-gcc"; reg = <0x0 0x00100000 0x0 0xc7018>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, <&pcie1_phy>, <0>, <0>, <0>, <0>, <0>, <0>; }; ipcc: mailbox@408000 { compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; reg = <0x0 0x408000 0x0 0x1000>; interrupts = ; interrupt-controller; #interrupt-cells = <3>; #mbox-cells = <2>; }; qfprom: efuse@784000 { compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; reg = <0x0 0x00784000 0x0 0x2410>; #address-cells = <1>; #size-cells = <1>; gpu_speed_bin: gpu-speed-bin@240c { reg = <0x240c 0x1>; bits = <0 8>; }; }; gpi_dma0: dma-controller@900000 { compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0x900000 0x0 0x60000>; #dma-cells = <3>; interrupts = , , , , , , , , , , , ; iommus = <&apps_smmu 0x416 0x0>; dma-channels = <12>; dma-channel-mask = <0xfff>; dma-coherent; status = "disabled"; }; qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x9c0000 0x0 0x2000>; ranges; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; #address-cells = <2>; #size-cells = <2>; iommus = <&apps_smmu 0x403 0x0>; dma-coherent; status = "disabled"; i2c0: i2c@980000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x980000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c0_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi0: spi@980000 { compatible = "qcom,geni-spi"; reg = <0x0 0x980000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart0: serial@980000 { compatible = "qcom,geni-uart"; reg = <0x0 0x980000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c1: i2c@984000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x984000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c1_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi1: spi@984000 { compatible = "qcom,geni-spi"; reg = <0x0 0x984000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart1: serial@984000 { compatible = "qcom,geni-uart"; reg = <0x0 0x984000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c2: i2c@988000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x988000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c2_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi2: spi@988000 { compatible = "qcom,geni-spi"; reg = <0x0 0x988000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart2: serial@988000 { compatible = "qcom,geni-uart"; reg = <0x0 0x988000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x98c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c3_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi3: spi@98c000 { compatible = "qcom,geni-spi"; reg = <0x0 0x98c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart3: serial@98c000 { compatible = "qcom,geni-uart"; reg = <0x0 0x98c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x990000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c4_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi4: spi@990000 { compatible = "qcom,geni-spi"; reg = <0x0 0x990000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart4: serial@990000 { compatible = "qcom,geni-uart"; reg = <0x0 0x990000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c5: i2c@994000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x994000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c5_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi5: spi@994000 { compatible = "qcom,geni-spi"; reg = <0x0 0x994000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart5: serial@994000 { compatible = "qcom,geni-uart"; reg = <0x0 0x994000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c6: i2c@998000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x998000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c6_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi6: spi@998000 { compatible = "qcom,geni-spi"; reg = <0x0 0x998000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart6: serial@998000 { compatible = "qcom,geni-uart"; reg = <0x0 0x998000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; uart7: serial@99c000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x0099c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; gpi_dma1: dma-controller@a00000 { compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0xa00000 0x0 0x60000>; #dma-cells = <3>; interrupts = , , , , , , , , , , , ; iommus = <&apps_smmu 0x456 0x0>; dma-channels = <12>; dma-channel-mask = <0xfff>; dma-coherent; status = "disabled"; }; qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0xac0000 0x0 0x2000>; ranges; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; #address-cells = <2>; #size-cells = <2>; iommus = <&apps_smmu 0x443 0x0>; dma-coherent; status = "disabled"; i2c8: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c8_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi8: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0x0 0xa80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart8: serial@a80000 { compatible = "qcom,geni-uart"; reg = <0x0 0xa80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa84000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c9_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi9: spi@a84000 { compatible = "qcom,geni-spi"; reg = <0x0 0xa84000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart9: serial@a84000 { compatible = "qcom,geni-uart"; reg = <0x0 0xa84000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa88000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c10_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi10: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0x0 0xa88000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart10: serial@a88000 { compatible = "qcom,geni-uart"; reg = <0x0 0xa88000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa8c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c11_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; uart11: serial@a8c000 { compatible = "qcom,geni-uart"; reg = <0x0 0xa8c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c12: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa90000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c12_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi12: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0x0 0xa90000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart12: serial@a90000 { compatible = "qcom,geni-uart"; reg = <0x0 0xa90000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa94000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c13_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi13: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0x0 0xa94000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart13: serial@a94000 { compatible = "qcom,geni-uart"; reg = <0x0 0xa94000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c14: i2c@a98000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa98000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c14_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi14: spi@a98000 { compatible = "qcom,geni-spi"; reg = <0x0 0xa98000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart14: serial@a98000 { compatible = "qcom,geni-uart"; reg = <0x0 0xa98000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c15: i2c@a9c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa9c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c15_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi15: spi@a9c000 { compatible = "qcom,geni-spi"; reg = <0x0 0xa9c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, <&gpi_dma1 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart15: serial@a9c000 { compatible = "qcom,geni-uart"; reg = <0x0 0xa9c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; gpi_dma3: dma-controller@b00000 { compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0xb00000 0x0 0x60000>; #dma-cells = <3>; interrupts = , , , ; iommus = <&apps_smmu 0x56 0x0>; dma-channels = <4>; dma-channel-mask = <0xf>; dma-coherent; status = "disabled"; }; qupv3_id_3: geniqup@bc0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0xbc0000 0x0 0x2000>; ranges; clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; #address-cells = <2>; #size-cells = <2>; iommus = <&apps_smmu 0x43 0x0>; dma-coherent; status = "disabled"; i2c16: i2c@b80000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xb80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c16_data_clk>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, <&gpi_dma3 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi16: spi@b80000 { compatible = "qcom,geni-spi"; reg = <0x0 0xb80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; pinctrl-names = "default"; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, <&gpi_dma3 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart16: serial@b80000 { compatible = "qcom,geni-uart"; reg = <0x0 0xb80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, <&qup_uart16_tx>, <&qup_uart16_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; rng: rng@10d2000 { compatible = "qcom,qcs8300-trng", "qcom,trng"; reg = <0x0 0x010d2000 0x0 0x1000>; }; config_noc: interconnect@14c0000 { compatible = "qcom,qcs8300-config-noc"; reg = <0x0 0x014c0000 0x0 0x13080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1680000 { compatible = "qcom,qcs8300-system-noc"; reg = <0x0 0x01680000 0x0 0x15080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16c0000 { compatible = "qcom,qcs8300-aggre1-noc"; reg = <0x0 0x016c0000 0x0 0x17080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,qcs8300-aggre2-noc"; reg = <0x0 0x01700000 0x0 0x1a080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; pcie_anoc: interconnect@1760000 { compatible = "qcom,qcs8300-pcie-anoc"; reg = <0x0 0x01760000 0x0 0xc080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gpdsp_anoc: interconnect@1780000 { compatible = "qcom,qcs8300-gpdsp-anoc"; reg = <0x0 0x01780000 0x0 0xd080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@17a0000 { compatible = "qcom,qcs8300-mmss-noc"; reg = <0x0 0x017a0000 0x0 0x40000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; pcie0: pci@1c00000 { device_type = "pci"; compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; reg = <0x0 0x01c00000 0x0 0x3000>, <0x0 0x40000000 0x0 0xf20>, <0x0 0x40000f20 0x0 0xa8>, <0x0 0x40001000 0x0 0x4000>, <0x0 0x40100000 0x0 0x100000>, <0x0 0x01c03000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; bus-range = <0x00 0xff>; dma-coherent; linux,pci-domain = <0>; num-lanes = <2>; interrupts = , , , , , , , , ; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a"; assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; assigned-clock-rates = <19200000>; interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, <0x100 &pcie_smmu 0x0001 0x1>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; reset-names = "pci", "link_down"; power-domains = <&gcc GCC_PCIE_0_GDSC>; eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55>; operating-points-v2 = <&pcie0_opp_table>; status = "disabled"; pcie0_opp_table: opp-table { compatible = "operating-points-v2"; /* GEN 1 x1 */ opp-2500000 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <250000 1>; }; /* GEN 1 x2 and GEN 2 x1 */ opp-5000000 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <500000 1>; }; /* GEN 2 x2 */ opp-10000000 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <1000000 1>; }; /* GEN 3 x1 */ opp-8000000 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <984500 1>; }; /* GEN 3 x2 and GEN 4 x1 */ opp-16000000 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; }; /* GEN 4 x2 */ opp-32000000 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <3938000 1>; }; }; pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; phys = <&pcie0_phy>; }; }; pcie0_phy: phy@1c04000 { compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; reg = <0x0 0x01c04000 0x0 0x2000>; clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; #clock-cells = <0>; clock-output-names = "pcie_0_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; pcie1: pci@1c10000 { device_type = "pci"; compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; reg = <0x0 0x01c10000 0x0 0x3000>, <0x0 0x60000000 0x0 0xf20>, <0x0 0x60000f20 0x0 0xa8>, <0x0 0x60001000 0x0 0x4000>, <0x0 0x60100000 0x0 0x100000>, <0x0 0x01c13000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; bus-range = <0x00 0xff>; dma-coherent; linux,pci-domain = <1>; num-lanes = <4>; interrupts = , , , , , , , , ; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, <0x100 &pcie_smmu 0x0081 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; reset-names = "pci", "link_down"; power-domains = <&gcc GCC_PCIE_1_GDSC>; eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; operating-points-v2 = <&pcie1_opp_table>; status = "disabled"; pcie1_opp_table: opp-table { compatible = "operating-points-v2"; /* GEN 1 x1 */ opp-2500000 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <250000 1>; }; /* GEN 1 x2 and GEN 2 x1 */ opp-5000000 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <500000 1>; }; /* GEN 1 x4 and GEN 2 x2 */ opp-10000000 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <1000000 1>; }; /* GEN 2 x4 */ opp-20000000 { opp-hz = /bits/ 64 <20000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <2000000 1>; }; /* GEN 3 x1 */ opp-8000000 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <984500 1>; }; /* GEN 3 x2 and GEN 4 x1 */ opp-16000000 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; }; /* GEN 3 x4 and GEN 4 x2 */ opp-32000000 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <3938000 1>; }; /* GEN 4 x4 */ opp-64000000 { opp-hz = /bits/ 64 <64000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <7876000 1>; }; }; pcieport1: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; phys = <&pcie1_phy>; }; }; pcie1_phy: phy@1c14000 { compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg = <0x0 0x01c14000 0x0 0x4000>; clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; #clock-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; ufs_mem_hc: ufs@1d84000 { compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; interrupts = ; phys = <&ufs_mem_phy>; phy-names = "ufsphy"; lanes-per-direction = <2>; #reset-cells = <1>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; required-opps = <&rpmhpd_opp_nom>; iommus = <&apps_smmu 0x100 0x0>; dma-coherent; interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; interconnect-names = "ufs-ddr", "cpu-ufs"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; freq-table-hz = <75000000 300000000>, <0 0>, <0 0>, <75000000 300000000>, <0 0>, <0 0>, <0 0>, <0 0>; qcom,ice = <&ice>; status = "disabled"; }; ufs_mem_phy: phy@1d87000 { compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; reg = <0x0 0x01d87000 0x0 0xe10>; /* * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It * enables the CXO clock to eDP *and* UFS PHY. */ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "ref", "ref_aux", "qref"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; #phy-cells = <0>; status = "disabled"; }; cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; interrupts = ; #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; num-channels = <20>; qcom,num-ees = <4>; iommus = <&apps_smmu 0x480 0x00>, <&apps_smmu 0x481 0x00>; }; ice: crypto@1d88000 { compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; crypto: crypto@1dfa000 { compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce"; reg = <0x0 0x01dfa000 0x0 0x6000>; dmas = <&cryptobam 4>, <&cryptobam 5>; dma-names = "rx", "tx"; iommus = <&apps_smmu 0x480 0x0>, <&apps_smmu 0x481 0x0>; interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "memory"; }; tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; }; tcsr: syscon@1fc0000 { compatible = "qcom,qcs8300-tcsr", "syscon"; reg = <0x0 0x1fc0000 0x0 0x30000>; }; remoteproc_adsp: remoteproc@3000000 { compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; reg = <0x0 0x3000000 0x0 0x00100>; interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd RPMHPD_LCX>, <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&adsp_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; remoteproc_adsp_glink: glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "lpass"; qcom,remote-pid = <2>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; memory-region = <&adsp_rpc_remote_heap_mem>; qcom,vmids = ; #address-cells = <1>; #size-cells = <0>; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x2003 0x0>; dma-coherent; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x2004 0x0>; dma-coherent; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x2005 0x0>; dma-coherent; }; }; gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; qcom,domain = ; qcom,intents = <512 20>; #address-cells = <1>; #size-cells = <0>; q6apm: service@1 { compatible = "qcom,q6apm"; reg = ; #sound-dai-cells = <0>; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; q6apmbedai: bedais { compatible = "qcom,q6apm-lpass-dais"; #sound-dai-cells = <1>; }; q6apmdai: dais { compatible = "qcom,q6apm-dais"; iommus = <&apps_smmu 0x2001 0x0>; }; }; q6prm: service@2 { compatible = "qcom,q6prm"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; q6prmcc: clock-controller { compatible = "qcom,q6prm-lpass-clocks"; #clock-cells = <2>; }; }; }; }; }; lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,qcs8300-lpass-ag-noc"; reg = <0x0 0x03c40000 0x0 0x17200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; ctcu@4001000 { compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu"; reg = <0x0 0x04001000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; ctcu_in0: endpoint { remote-endpoint = <&etr0_out>; }; }; port@1 { reg = <1>; ctcu_in1: endpoint { remote-endpoint = <&etr1_out>; }; }; }; }; stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x04002000 0x0 0x1000>, <0x0 0x16280000 0x0 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { stm_out: endpoint { remote-endpoint = <&funnel0_in7>; }; }; }; }; tpda@4004000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x04004000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; swao_rep_out0: endpoint { remote-endpoint = <&qdss_rep_in>; }; }; port@1 { reg = <1>; qdss_tpda_in1: endpoint { remote-endpoint = <&qdss_tpdm1_out>; }; }; }; out-ports { port { qdss_tpda_out: endpoint { remote-endpoint = <&funnel0_in6>; }; }; }; }; tpdm@400f000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x0400f000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; out-ports { port { qdss_tpdm1_out: endpoint { remote-endpoint = <&qdss_tpda_in1>; }; }; }; }; funnel@4041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04041000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@6 { reg = <6>; funnel0_in6: endpoint { remote-endpoint = <&qdss_tpda_out>; }; }; port@7 { reg = <7>; funnel0_in7: endpoint { remote-endpoint = <&stm_out>; }; }; }; out-ports { port { funnel0_out: endpoint { remote-endpoint = <&qdss_funnel_in0>; }; }; }; }; funnel@4042000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04042000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@4 { reg = <4>; funnel1_in4: endpoint { remote-endpoint = <&apss_funnel1_out>; }; }; port@5 { reg = <5>; funnel1_in5: endpoint { remote-endpoint = <&dlct0_funnel_out>; }; }; port@6 { reg = <6>; funnel1_in6: endpoint { remote-endpoint = <&dlmm_funnel_out>; }; }; port@7 { reg = <7>; funnel1_in7: endpoint { remote-endpoint = <&dlst_ch_funnel_out>; }; }; }; out-ports { port { funnel1_out: endpoint { remote-endpoint = <&qdss_funnel_in1>; }; }; }; }; funnel@4045000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04045000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; qdss_funnel_in0: endpoint { remote-endpoint = <&funnel0_out>; }; }; port@1 { reg = <1>; qdss_funnel_in1: endpoint { remote-endpoint = <&funnel1_out>; }; }; }; out-ports { port { qdss_funnel_out: endpoint { remote-endpoint = <&aoss_funnel_in7>; }; }; }; }; replicator@4046000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0x0 0x04046000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { qdss_rep_in: endpoint { remote-endpoint = <&swao_rep_out0>; }; }; }; out-ports { port { qdss_rep_out0: endpoint { remote-endpoint = <&etr_rep_in>; }; }; }; }; tmc@4048000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x0 0x04048000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; iommus = <&apps_smmu 0x04c0 0x00>; arm,scatter-gather; in-ports { port { etr0_in: endpoint { remote-endpoint = <&etr_rep_out0>; }; }; }; out-ports { port { etr0_out: endpoint { remote-endpoint = <&ctcu_in0>; }; }; }; }; replicator@404e000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0x0 0x0404e000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { etr_rep_in: endpoint { remote-endpoint = <&qdss_rep_out0>; }; }; }; out-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; etr_rep_out0: endpoint { remote-endpoint = <&etr0_in>; }; }; port@1 { reg = <1>; etr_rep_out1: endpoint { remote-endpoint = <&etr1_in>; }; }; }; }; tmc@404f000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x0 0x0404f000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; iommus = <&apps_smmu 0x04a0 0x40>; arm,scatter-gather; arm,buffer-size = <0x400000>; in-ports { port { etr1_in: endpoint { remote-endpoint = <&etr_rep_out1>; }; }; }; out-ports { port { etr1_out: endpoint { remote-endpoint = <&ctcu_in1>; }; }; }; }; tpdm@4841000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04841000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; out-ports { port { prng_tpdm_out: endpoint { remote-endpoint = <&dlct0_tpda_in19>; }; }; }; }; tpdm@4850000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04850000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { pimem_tpdm_out: endpoint { remote-endpoint = <&dlct0_tpda_in25>; }; }; }; }; tpdm@4860000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04860000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { dlst_ch_tpdm0_out: endpoint { remote-endpoint = <&dlst_ch_tpda_in8>; }; }; }; }; tpda@4864000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x04864000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@8 { reg = <8>; dlst_ch_tpda_in8: endpoint { remote-endpoint = <&dlst_ch_tpdm0_out>; }; }; }; out-ports { port { dlst_ch_tpda_out: endpoint { remote-endpoint = <&dlst_ch_funnel_in0>; }; }; }; }; funnel@4865000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04865000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dlst_ch_funnel_in0: endpoint { remote-endpoint = <&dlst_ch_tpda_out>; }; }; port@4 { reg = <4>; dlst_ch_funnel_in4: endpoint { remote-endpoint = <&dlst_funnel_out>; }; }; port@6 { reg = <6>; dlst_ch_funnel_in6: endpoint { remote-endpoint = <&gdsp_funnel_out>; }; }; }; out-ports { port { dlst_ch_funnel_out: endpoint { remote-endpoint = <&funnel1_in7>; }; }; }; }; tpdm@4980000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04980000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { turing2_tpdm_out: endpoint { remote-endpoint = <&turing2_funnel_in0>; }; }; }; }; funnel@4983000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04983000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { turing2_funnel_in0: endpoint { remote-endpoint = <&turing2_tpdm_out>; }; }; }; out-ports { port { turing2_funnel_out0: endpoint { remote-endpoint = <&gdsp_tpda_in5>; }; }; }; }; tpdm@4ac0000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04ac0000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { dlmm_tpdm0_out: endpoint { remote-endpoint = <&dlmm_tpda_in27>; }; }; }; }; tpda@4ac4000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x04ac4000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@1b { reg = <27>; dlmm_tpda_in27: endpoint { remote-endpoint = <&dlmm_tpdm0_out>; }; }; }; out-ports { port { dlmm_tpda_out: endpoint { remote-endpoint = <&dlmm_funnel_in0>; }; }; }; }; funnel@4ac5000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04ac5000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { dlmm_funnel_in0: endpoint { remote-endpoint = <&dlmm_tpda_out>; }; }; }; out-ports { port { dlmm_funnel_out: endpoint { remote-endpoint = <&funnel1_in6>; }; }; }; }; tpdm@4ad0000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04ad0000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { dlct0_tpdm0_out: endpoint { remote-endpoint = <&dlct0_tpda_in26>; }; }; }; }; tpda@4ad3000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x04ad3000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@13 { reg = <19>; dlct0_tpda_in19: endpoint { remote-endpoint = <&prng_tpdm_out>; }; }; port@19 { reg = <25>; dlct0_tpda_in25: endpoint { remote-endpoint = <&pimem_tpdm_out>; }; }; port@1a { reg = <26>; dlct0_tpda_in26: endpoint { remote-endpoint = <&dlct0_tpdm0_out>; }; }; }; out-ports { port { dlct0_tpda_out: endpoint { remote-endpoint = <&dlct0_funnel_in0>; }; }; }; }; funnel@4ad4000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04ad4000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dlct0_funnel_in0: endpoint { remote-endpoint = <&dlct0_tpda_out>; }; }; port@4 { reg = <4>; dlct0_funnel_in4: endpoint { remote-endpoint = <&ddr_funnel5_out>; }; }; }; out-ports { port { dlct0_funnel_out: endpoint { remote-endpoint = <&funnel1_in5>; }; }; }; }; funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04b04000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@6 { reg = <6>; aoss_funnel_in6: endpoint { remote-endpoint = <&aoss_tpda_out>; }; }; port@7 { reg = <7>; aoss_funnel_in7: endpoint { remote-endpoint = <&qdss_funnel_out>; }; }; }; out-ports { port { aoss_funnel_out: endpoint { remote-endpoint = <&etf0_in>; }; }; }; }; tmc_etf: tmc@4b05000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x0 0x04b05000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { etf0_in: endpoint { remote-endpoint = <&aoss_funnel_out>; }; }; }; out-ports { port { etf0_out: endpoint { remote-endpoint = <&swao_rep_in>; }; }; }; }; replicator@4b06000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0x0 0x04b06000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { swao_rep_in: endpoint { remote-endpoint = <&etf0_out>; }; }; }; out-ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; swao_rep_out1: endpoint { remote-endpoint = <&eud_in>; }; }; }; }; tpda@4b08000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x04b08000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; aoss_tpda_in0: endpoint { remote-endpoint = <&aoss_tpdm0_out>; }; }; port@1 { reg = <1>; aoss_tpda_in1: endpoint { remote-endpoint = <&aoss_tpdm1_out>; }; }; port@2 { reg = <2>; aoss_tpda_in2: endpoint { remote-endpoint = <&aoss_tpdm2_out>; }; }; port@3 { reg = <3>; aoss_tpda_in3: endpoint { remote-endpoint = <&aoss_tpdm3_out>; }; }; port@4 { reg = <4>; aoss_tpda_in4: endpoint { remote-endpoint = <&aoss_tpdm4_out>; }; }; }; out-ports { port { aoss_tpda_out: endpoint { remote-endpoint = <&aoss_funnel_in6>; }; }; }; }; tpdm@4b09000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04b09000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; out-ports { port { aoss_tpdm0_out: endpoint { remote-endpoint = <&aoss_tpda_in0>; }; }; }; }; tpdm@4b0a000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04b0a000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; out-ports { port { aoss_tpdm1_out: endpoint { remote-endpoint = <&aoss_tpda_in1>; }; }; }; }; tpdm@4b0b000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04b0b000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; out-ports { port { aoss_tpdm2_out: endpoint { remote-endpoint = <&aoss_tpda_in2>; }; }; }; }; tpdm@4b0c000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04b0c000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; out-ports { port { aoss_tpdm3_out: endpoint { remote-endpoint = <&aoss_tpda_in3>; }; }; }; }; tpdm@4b0d000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04b0d000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { aoss_tpdm4_out: endpoint { remote-endpoint = <&aoss_tpda_in4>; }; }; }; }; cti@4b13000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x0 0x04b13000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; tpdm@4b80000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04b80000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { turing0_tpdm0_out: endpoint { remote-endpoint = <&turing0_tpda_in0>; }; }; }; }; tpda@4b86000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x04b86000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { turing0_tpda_in0: endpoint { remote-endpoint = <&turing0_tpdm0_out>; }; }; }; out-ports { port { turing0_tpda_out: endpoint { remote-endpoint = <&turing0_funnel_in0>; }; }; }; }; funnel@4b87000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04b87000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { turing0_funnel_in0: endpoint { remote-endpoint = <&turing0_tpda_out>; }; }; }; out-ports { port { turing0_funnel_out: endpoint { remote-endpoint = <&gdsp_funnel_in4>; }; }; }; }; cti@4b8b000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x0 0x04b8b000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; tpdm@4c40000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04c40000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { gdsp_tpdm0_out: endpoint { remote-endpoint = <&gdsp_tpda_in8>; }; }; }; }; tpda@4c44000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x04c44000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@5 { reg = <5>; gdsp_tpda_in5: endpoint { remote-endpoint = <&turing2_funnel_out0>; }; }; port@8 { reg = <8>; gdsp_tpda_in8: endpoint { remote-endpoint = <&gdsp_tpdm0_out>; }; }; }; out-ports { port { gdsp_tpda_out: endpoint { remote-endpoint = <&gdsp_funnel_in0>; }; }; }; }; funnel@4c45000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04c45000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; gdsp_funnel_in0: endpoint { remote-endpoint = <&gdsp_tpda_out>; }; }; port@4 { reg = <4>; gdsp_funnel_in4: endpoint { remote-endpoint = <&turing0_funnel_out>; }; }; }; out-ports { port { gdsp_funnel_out: endpoint { remote-endpoint = <&dlst_ch_funnel_in6>; }; }; }; }; tpdm@4c50000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04c50000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { dlst_tpdm0_out: endpoint { remote-endpoint = <&dlst_tpda_in8>; }; }; }; }; tpda@4c54000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x04c54000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@8 { reg = <8>; dlst_tpda_in8: endpoint { remote-endpoint = <&dlst_tpdm0_out>; }; }; }; out-ports { port { dlst_tpda_out: endpoint { remote-endpoint = <&dlst_funnel_in0>; }; }; }; }; funnel@4c55000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04c55000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { dlst_funnel_in0: endpoint { remote-endpoint = <&dlst_tpda_out>; }; }; }; out-ports { port { dlst_funnel_out: endpoint { remote-endpoint = <&dlst_ch_funnel_in4>; }; }; }; }; tpdm@4e00000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04e00000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; out-ports { port { ddr_tpdm3_out: endpoint { remote-endpoint = <&ddr_tpda_in4>; }; }; }; }; tpda@4e03000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x04e03000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; ddr_tpda_in0: endpoint { remote-endpoint = <&ddr_funnel0_out0>; }; }; port@1 { reg = <1>; ddr_tpda_in1: endpoint { remote-endpoint = <&ddr_funnel1_out0>; }; }; port@4 { reg = <4>; ddr_tpda_in4: endpoint { remote-endpoint = <&ddr_tpdm3_out>; }; }; }; out-ports { port { ddr_tpda_out: endpoint { remote-endpoint = <&ddr_funnel5_in0>; }; }; }; }; funnel@4e04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04e04000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { ddr_funnel5_in0: endpoint { remote-endpoint = <&ddr_tpda_out>; }; }; }; out-ports { port { ddr_funnel5_out: endpoint { remote-endpoint = <&dlct0_funnel_in4>; }; }; }; }; tpdm@4e10000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04e10000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { ddr_tpdm0_out: endpoint { remote-endpoint = <&ddr_funnel0_in0>; }; }; }; }; funnel@4e12000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04e12000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { ddr_funnel0_in0: endpoint { remote-endpoint = <&ddr_tpdm0_out>; }; }; }; out-ports { port { ddr_funnel0_out0: endpoint { remote-endpoint = <&ddr_tpda_in0>; }; }; }; }; tpdm@4e20000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04e20000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { ddr_tpdm1_out: endpoint { remote-endpoint = <&ddr_funnel1_in0>; }; }; }; }; funnel@4e22000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x04e22000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { port { ddr_funnel1_in0: endpoint { remote-endpoint = <&ddr_tpdm1_out>; }; }; }; out-ports { port { ddr_funnel1_out0: endpoint { remote-endpoint = <&ddr_tpda_in1>; }; }; }; }; etm@6040000 { compatible = "arm,primecell"; reg = <0x0 0x06040000 0x0 0x1000>; cpu = <&cpu0>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm0_out: endpoint { remote-endpoint = <&apss_funnel0_in0>; }; }; }; }; etm@6140000 { compatible = "arm,primecell"; reg = <0x0 0x06140000 0x0 0x1000>; cpu = <&cpu1>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm1_out: endpoint { remote-endpoint = <&apss_funnel0_in1>; }; }; }; }; etm@6240000 { compatible = "arm,primecell"; reg = <0x0 0x06240000 0x0 0x1000>; cpu = <&cpu2>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm2_out: endpoint { remote-endpoint = <&apss_funnel0_in2>; }; }; }; }; etm@6340000 { compatible = "arm,primecell"; reg = <0x0 0x06340000 0x0 0x1000>; cpu = <&cpu3>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm3_out: endpoint { remote-endpoint = <&apss_funnel0_in3>; }; }; }; }; etm@6440000 { compatible = "arm,primecell"; reg = <0x0 0x06440000 0x0 0x1000>; cpu = <&cpu4>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm4_out: endpoint { remote-endpoint = <&apss_funnel0_in4>; }; }; }; }; etm@6540000 { compatible = "arm,primecell"; reg = <0x0 0x06540000 0x0 0x1000>; cpu = <&cpu5>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm5_out: endpoint { remote-endpoint = <&apss_funnel0_in5>; }; }; }; }; etm@6640000 { compatible = "arm,primecell"; reg = <0x0 0x06640000 0x0 0x1000>; cpu = <&cpu6>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm6_out: endpoint { remote-endpoint = <&apss_funnel0_in6>; }; }; }; }; etm@6740000 { compatible = "arm,primecell"; reg = <0x0 0x06740000 0x0 0x1000>; cpu = <&cpu7>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm7_out: endpoint { remote-endpoint = <&apss_funnel0_in7>; }; }; }; }; funnel@6800000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x06800000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; apss_funnel0_in0: endpoint { remote-endpoint = <&etm0_out>; }; }; port@1 { reg = <1>; apss_funnel0_in1: endpoint { remote-endpoint = <&etm1_out>; }; }; port@2 { reg = <2>; apss_funnel0_in2: endpoint { remote-endpoint = <&etm2_out>; }; }; port@3 { reg = <3>; apss_funnel0_in3: endpoint { remote-endpoint = <&etm3_out>; }; }; port@4 { reg = <4>; apss_funnel0_in4: endpoint { remote-endpoint = <&etm4_out>; }; }; port@5 { reg = <5>; apss_funnel0_in5: endpoint { remote-endpoint = <&etm5_out>; }; }; port@6 { reg = <6>; apss_funnel0_in6: endpoint { remote-endpoint = <&etm6_out>; }; }; port@7 { reg = <7>; apss_funnel0_in7: endpoint { remote-endpoint = <&etm7_out>; }; }; }; out-ports { port { apss_funnel0_out: endpoint { remote-endpoint = <&apss_funnel1_in0>; }; }; }; }; funnel@6810000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x06810000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; apss_funnel1_in0: endpoint { remote-endpoint = <&apss_funnel0_out>; }; }; port@3 { reg = <3>; apss_funnel1_in3: endpoint { remote-endpoint = <&apss_tpda_out>; }; }; }; out-ports { port { apss_funnel1_out: endpoint { remote-endpoint = <&funnel1_in4>; }; }; }; }; cti@682b000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x0 0x0682b000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; tpdm@6860000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x06860000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; out-ports { port { apss_tpdm3_out: endpoint { remote-endpoint = <&apss_tpda_in3>; }; }; }; }; tpdm@6861000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x06861000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { apss_tpdm4_out: endpoint { remote-endpoint = <&apss_tpda_in4>; }; }; }; }; tpda@6863000 { compatible = "qcom,coresight-tpda", "arm,primecell"; reg = <0x0 0x06863000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; apss_tpda_in0: endpoint { remote-endpoint = <&apss_tpdm0_out>; }; }; port@1 { reg = <1>; apss_tpda_in1: endpoint { remote-endpoint = <&apss_tpdm1_out>; }; }; port@2 { reg = <2>; apss_tpda_in2: endpoint { remote-endpoint = <&apss_tpdm2_out>; }; }; port@3 { reg = <3>; apss_tpda_in3: endpoint { remote-endpoint = <&apss_tpdm3_out>; }; }; port@4 { reg = <4>; apss_tpda_in4: endpoint { remote-endpoint = <&apss_tpdm4_out>; }; }; }; out-ports { port { apss_tpda_out: endpoint { remote-endpoint = <&apss_funnel1_in3>; }; }; }; }; tpdm@68a0000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x068a0000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; out-ports { port { apss_tpdm1_out: endpoint { remote-endpoint = <&apss_tpda_in1>; }; }; }; }; tpdm@68b0000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x068b0000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; out-ports { port { apss_tpdm0_out: endpoint { remote-endpoint = <&apss_tpda_in0>; }; }; }; }; tpdm@68c0000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x068c0000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; out-ports { port { apss_tpdm2_out: endpoint { remote-endpoint = <&apss_tpda_in2>; }; }; }; }; cti@68e0000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x0 0x068e0000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; cti@68f0000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x0 0x068f0000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; cti@6900000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x0 0x06900000 0x0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; sdhc_1: mmc@87c4000 { compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x087c4000 0x0 0x1000>, <0x0 0x087c5000 0x0 0x1000>; reg-names = "hc", "cqhci"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC1_BCR>; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc1_opp_table>; iommus = <&apps_smmu 0x0 0x0>; interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; qcom,dll-config = <0x000f64ee>; qcom,ddr-config = <0x80040868>; supports-cqe; dma-coherent; status = "disabled"; sdhc1_opp_table: opp-table { compatible = "operating-points-v2"; opp-50000000 { opp-hz = /bits/ 64 <50000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; usb_1_hsphy: phy@8904000 { compatible = "qcom,qcs8300-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; reg = <0x0 0x08904000 0x0 0x400>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; #phy-cells = <0>; status = "disabled"; }; usb_2_hsphy: phy@8906000 { compatible = "qcom,qcs8300-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; reg = <0x0 0x08906000 0x0 0x400>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_USB2_PHY_SEC_BCR>; #phy-cells = <0>; status = "disabled"; }; usb_qmpphy: phy@8907000 { compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; reg = <0x0 0x08907000 0x0 0x2000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB_CLKREF_EN>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", "pipe"; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; reset-names = "phy", "phy_phy"; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; #clock-cells = <0>; clock-output-names = "usb3_prim_phy_pipe_clk_src"; #phy-cells = <0>; status = "disabled"; }; serdes0: phy@8909000 { compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; reg = <0x0 0x08909000 0x0 0x00000e10>; clocks = <&gcc GCC_SGMI_CLKREF_EN>; clock-names = "sgmi_ref"; #phy-cells = <0>; status = "disabled"; }; refgen: regulator@891c000 { compatible = "qcom,qcs8300-refgen-regulator", "qcom,sm8250-refgen-regulator"; reg = <0x0 0x0891c000 0x0 0x84>; }; gpu: gpu@3d00000 { compatible = "qcom,adreno-623.0", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, <0x0 0x03d9e000 0x0 0x1000>, <0x0 0x03d61000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; interrupts = ; iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "gfx-mem"; #cooling-cells = <2>; nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; status = "disabled"; gpu_zap_shader: zap-shader { memory-region = <&gpu_microcode_mem>; }; gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-877000000 { opp-hz = /bits/ 64 <877000000>; opp-level = ; opp-peak-kBps = <12484375>; opp-supported-hw = <0x1>; }; opp-780000000 { opp-hz = /bits/ 64 <780000000>; opp-level = ; opp-peak-kBps = <10687500>; opp-supported-hw = <0x1>; }; opp-599000000 { opp-hz = /bits/ 64 <599000000>; opp-level = ; opp-peak-kBps = <8171875>; opp-supported-hw = <0x3>; }; opp-479000000 { opp-hz = /bits/ 64 <479000000>; opp-level = ; opp-peak-kBps = <5285156>; opp-supported-hw = <0x3>; }; }; }; gmu: gmu@3d6a000 { compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; reg = <0x0 0x03d6a000 0x0 0x34000>, <0x0 0x03de0000 0x0 0x10000>, <0x0 0x0b290000 0x0 0x10000>; reg-names = "gmu", "rscc", "gmu_pdc"; interrupts = , ; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>; clock-names = "gmu", "cxo", "axi", "memnoc", "ahb", "hub"; power-domains = <&gpucc GPU_CC_CX_GDSC>, <&gpucc GPU_CC_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5 0xc00>; operating-points-v2 = <&gmu_opp_table>; gmu_opp_table: opp-table { compatible = "operating-points-v2"; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-level = ; }; }; }; gpucc: clock-controller@3d90000 { compatible = "qcom,qcs8300-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; adreno_smmu: iommu@3da0000 { compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x3da0000 0x0 0x20000>; #iommu-cells = <2>; #global-interrupts = <2>; interrupts = , , , , , , , , , , , ; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>, <&gpucc GPU_CC_HUB_AON_CLK>; clock-names = "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", "gpu_cc_ahb_clk", "gpu_cc_hlos1_vote_gpu_smmu_clk", "gpu_cc_cx_gmu_clk", "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; power-domains = <&gpucc GPU_CC_CX_GDSC>; dma-coherent; }; pmu@9091000 { compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x9091000 0x0 0x1000>; interrupts = ; interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; operating-points-v2 = <&llcc_bwmon_opp_table>; llcc_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; opp-0 { opp-peak-kBps = <762000>; }; opp-1 { opp-peak-kBps = <1720000>; }; opp-2 { opp-peak-kBps = <2086000>; }; opp-3 { opp-peak-kBps = <2601000>; }; opp-4 { opp-peak-kBps = <2929000>; }; opp-5 { opp-peak-kBps = <5931000>; }; opp-6 { opp-peak-kBps = <6515000>; }; opp-7 { opp-peak-kBps = <7984000>; }; opp-8 { opp-peak-kBps = <10437000>; }; opp-9 { opp-peak-kBps = <12195000>; }; }; }; pmu@90b5400 { compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0x0 0x90b5400 0x0 0x600>; interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; operating-points-v2 = <&cpu_bwmon_opp_table>; cpu_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; opp-0 { opp-peak-kBps = <9155000>; }; opp-1 { opp-peak-kBps = <12298000>; }; opp-2 { opp-peak-kBps = <14236000>; }; opp-3 { opp-peak-kBps = <16265000>; }; }; }; pmu@90b6400 { compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0x0 0x90b6400 0x0 0x600>; interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; operating-points-v2 = <&cpu_bwmon_opp_table>; }; dc_noc: interconnect@90e0000 { compatible = "qcom,qcs8300-dc-noc"; reg = <0x0 0x090e0000 0x0 0x5080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9100000 { compatible = "qcom,qcs8300-gem-noc"; reg = <0x0 0x9100000 0x0 0xf7080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; llcc: system-cache-controller@9200000 { compatible = "qcom,qcs8300-llcc"; reg = <0x0 0x09200000 0x0 0x80000>, <0x0 0x09300000 0x0 0x80000>, <0x0 0x09400000 0x0 0x80000>, <0x0 0x09500000 0x0 0x80000>, <0x0 0x09a00000 0x0 0x80000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; usb_1: usb@a600000 { compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; reg = <0x0 0x0a600000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "usb-ddr", "apps-usb"; iommus = <&apps_smmu 0x80 0x0>; phys = <&usb_1_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; wakeup-source; status = "disabled"; }; usb_2: usb@a400000 { compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; reg = <0x0 0x0a400000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, <&gcc GCC_USB20_MASTER_CLK>, <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, <&gcc GCC_USB20_SLEEP_CLK>, <&gcc GCC_USB20_MOCK_UTMI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; power-domains = <&gcc GCC_USB20_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB20_PRIM_BCR>; interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "usb-ddr", "apps-usb"; iommus = <&apps_smmu 0x20 0x0>; phys = <&usb_2_hsphy>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; qcom,select-utmi-as-pipe-clk; wakeup-source; status = "disabled"; }; iris: video-codec@aa00000 { compatible = "qcom,qcs8300-iris"; reg = <0x0 0x0aa00000 0x0 0xf0000>; interrupts = ; power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, <&videocc VIDEO_CC_MVS0_GDSC>, <&rpmhpd RPMHPD_MX>, <&rpmhpd RPMHPD_MMCX>; power-domain-names = "venus", "vcodec0", "mxc", "mmcx"; operating-points-v2 = <&iris_opp_table>; clocks = <&gcc GCC_VIDEO_AXI0_CLK>, <&videocc VIDEO_CC_MVS0C_CLK>, <&videocc VIDEO_CC_MVS0_CLK>; clock-names = "iface", "core", "vcodec0_core"; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "cpu-cfg", "video-mem"; memory-region = <&video_mem>; resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; reset-names = "bus"; iommus = <&apps_smmu 0x0880 0x0400>, <&apps_smmu 0x0887 0x0400>; dma-coherent; status = "disabled"; iris_opp_table: opp-table { compatible = "operating-points-v2"; opp-366000000 { opp-hz = /bits/ 64 <366000000>; required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_svs_l1>; }; opp-444000000 { opp-hz = /bits/ 64 <444000000>; required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_nom>; }; opp-533000000 { opp-hz = /bits/ 64 <533000000>; required-opps = <&rpmhpd_opp_turbo>, <&rpmhpd_opp_turbo>; }; opp-560000000 { opp-hz = /bits/ 64 <560000000>; required-opps = <&rpmhpd_opp_turbo_l1>, <&rpmhpd_opp_turbo_l1>; }; }; }; videocc: clock-controller@abf0000 { compatible = "qcom,qcs8300-videocc"; reg = <0x0 0x0abf0000 0x0 0x10000>; clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; power-domains = <&rpmhpd RPMHPD_MMCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; camss: isp@ac78000 { compatible = "qcom,qcs8300-camss"; reg = <0x0 0xac78000 0x0 0x1000>, <0x0 0xac7a000 0x0 0xf00>, <0x0 0xac7c000 0x0 0xf00>, <0x0 0xac84000 0x0 0xf00>, <0x0 0xac88000 0x0 0xf00>, <0x0 0xac8c000 0x0 0xf00>, <0x0 0xac90000 0x0 0xf00>, <0x0 0xac94000 0x0 0xf00>, <0x0 0xac9c000 0x0 0x2000>, <0x0 0xac9e000 0x0 0x2000>, <0x0 0xaca0000 0x0 0x2000>, <0x0 0xacac000 0x0 0x400>, <0x0 0xacad000 0x0 0x400>, <0x0 0xacae000 0x0 0x400>, <0x0 0xac4d000 0x0 0xf000>, <0x0 0xac60000 0x0 0xf000>, <0x0 0xac85000 0x0 0xd00>, <0x0 0xac89000 0x0 0xd00>, <0x0 0xac8d000 0x0 0xd00>, <0x0 0xac91000 0x0 0xd00>, <0x0 0xac95000 0x0 0xd00>; reg-names = "csid_wrapper", "csid0", "csid1", "csid_lite0", "csid_lite1", "csid_lite2", "csid_lite3", "csid_lite4", "csiphy0", "csiphy1", "csiphy2", "tpg0", "tpg1", "tpg2", "vfe0", "vfe1", "vfe_lite0", "vfe_lite1", "vfe_lite2", "vfe_lite3", "vfe_lite4"; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CORE_AHB_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, <&camcc CAM_CC_CPAS_IFE_0_CLK>, <&camcc CAM_CC_CPAS_IFE_1_CLK>, <&camcc CAM_CC_CSID_CLK>, <&camcc CAM_CC_CSIPHY0_CLK>, <&camcc CAM_CC_CSI0PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY1_CLK>, <&camcc CAM_CC_CSI1PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY2_CLK>, <&camcc CAM_CC_CSI2PHYTIMER_CLK>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, <&gcc GCC_CAMERA_SF_AXI_CLK>, <&camcc CAM_CC_ICP_AHB_CLK>, <&camcc CAM_CC_IFE_0_CLK>, <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, <&camcc CAM_CC_IFE_1_CLK>, <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, <&camcc CAM_CC_IFE_LITE_CLK>, <&camcc CAM_CC_IFE_LITE_AHB_CLK>, <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, <&camcc CAM_CC_IFE_LITE_CSID_CLK>; clock-names = "camnoc_axi", "core_ahb", "cpas_ahb", "cpas_fast_ahb_clk", "cpas_vfe_lite", "cpas_vfe0", "cpas_vfe1", "csid", "csiphy0", "csiphy0_timer", "csiphy1", "csiphy1_timer", "csiphy2", "csiphy2_timer", "csiphy_rx", "gcc_axi_hf", "gcc_axi_sf", "icp_ahb", "vfe0", "vfe0_fast_ahb", "vfe1", "vfe1_fast_ahb", "vfe_lite", "vfe_lite_ahb", "vfe_lite_cphy_rx", "vfe_lite_csid"; interrupts = , , , , , , , , , , , , , , , , , , , ; interrupt-names = "csid0", "csid1", "csid_lite0", "csid_lite1", "csid_lite2", "csid_lite3", "csid_lite4", "csiphy0", "csiphy1", "csiphy2", "tpg0", "tpg1", "tpg2", "vfe0", "vfe1", "vfe_lite0", "vfe_lite1", "vfe_lite2", "vfe_lite3", "vfe_lite4"; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "ahb", "hf_0"; iommus = <&apps_smmu 0x2400 0x20>; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; power-domain-names = "top"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@1 { reg = <1>; }; port@2 { reg = <2>; }; }; }; camcc: clock-controller@ade0000 { compatible = "qcom,qcs8300-camcc"; reg = <0x0 0x0ade0000 0x0 0x20000>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; power-domains = <&rpmhpd RPMHPD_MMCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; mdss: display-subsystem@ae00000 { compatible = "qcom,qcs8300-mdss"; reg = <0x0 0x0ae00000 0x0 0x1000>; reg-names = "mdss"; interrupts = ; clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg"; power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; iommus = <&apps_smmu 0x1000 0x402>; interrupt-controller; #interrupt-cells = <1>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; mdss_mdp: display-controller@ae01000 { compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; reg = <0x0 0x0ae01000 0x0 0x8f000>, <0x0 0x0aeb0000 0x0 0x2008>; reg-names = "mdp", "vbif"; interrupts-extended = <&mdss 0>; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>, <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; clock-names = "nrt_bus", "iface", "lut", "core", "vsync"; assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dpu_intf0_out: endpoint { remote-endpoint = <&mdss_dp0_in>; }; }; }; mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-375000000 { opp-hz = /bits/ 64 <375000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; required-opps = <&rpmhpd_opp_nom>; }; opp-575000000 { opp-hz = /bits/ 64 <575000000>; required-opps = <&rpmhpd_opp_turbo>; }; opp-650000000 { opp-hz = /bits/ 64 <650000000>; required-opps = <&rpmhpd_opp_turbo_l1>; }; }; }; mdss_dp0_phy: phy@aec2a00 { compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; reg = <0x0 0x0aec2a00 0x0 0x19c>, <0x0 0x0aec2200 0x0 0xec>, <0x0 0x0aec2600 0x0 0xec>, <0x0 0x0aec2000 0x0 0x1c8>; clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; clock-names = "aux", "cfg_ahb"; power-domains = <&rpmhpd RPMHPD_MX>; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; mdss_dp0: displayport-controller@af54000 { compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp"; reg = <0x0 0x0af54000 0x0 0x200>, <0x0 0x0af54200 0x0 0x200>, <0x0 0x0af55000 0x0 0xc00>, <0x0 0x0af56000 0x0 0x09c>, <0x0 0x0af57000 0x0 0x09c>, <0x0 0x0af58000 0x0 0x09c>, <0x0 0x0af59000 0x0 0x09c>, <0x0 0x0af5a000 0x0 0x23c>, <0x0 0x0af5b000 0x0 0x23c>; interrupts-extended = <&mdss 12>; clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel", "stream_1_pixel", "stream_2_pixel", "stream_3_pixel"; assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; assigned-clock-parents = <&mdss_dp0_phy 0>, <&mdss_dp0_phy 1>, <&mdss_dp0_phy 1>, <&mdss_dp0_phy 1>, <&mdss_dp0_phy 1>; phys = <&mdss_dp0_phy>; phy-names = "dp"; operating-points-v2 = <&dp_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; #sound-dai-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss_dp0_in: endpoint { remote-endpoint = <&dpu_intf0_out>; }; }; port@1 { reg = <1>; mdss_dp0_out: endpoint { }; }; }; dp_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; }; dispcc: clock-controller@af00000 { compatible = "qcom,sa8775p-dispcc0"; reg = <0x0 0x0af00000 0x0 0x20000>; clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, <&mdss_dp0_phy 0>, <&mdss_dp0_phy 1>, <0>, <0>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; pdc: interrupt-controller@b220000 { compatible = "qcom,qcs8300-pdc", "qcom,pdc"; reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>; interrupt-parent = <&intc>; #interrupt-cells = <2>; interrupt-controller; qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, <59 312 3>, <62 374 2>, <64 434 2>, <66 438 2>, <70 520 1>, <73 523 1>, <118 568 6>, <124 609 3>, <159 638 1>, <160 720 3>, <169 728 30>, <199 416 2>, <201 449 1>, <202 89 1>, <203 451 1>, <204 462 1>, <205 264 1>, <206 579 1>, <207 653 1>, <208 656 1>, <209 659 1>, <210 122 1>, <211 699 1>, <212 705 1>, <213 450 1>, <214 643 2>, <216 646 5>, <221 390 5>, <226 700 2>, <228 440 1>, <229 663 1>, <230 524 2>, <232 612 3>, <235 723 5>; }; tsens2: thermal-sensor@c251000 { compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; reg = <0x0 0x0c251000 0x0 0x1000>, <0x0 0x0c224000 0x0 0x1000>; interrupts = , ; interrupt-names = "uplow", "critical"; #qcom,sensors = <10>; #thermal-sensor-cells = <1>; }; tsens3: thermal-sensor@c252000 { compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; reg = <0x0 0x0c252000 0x0 0x1000>, <0x0 0x0c225000 0x0 0x1000>; interrupts = , ; interrupt-names = "uplow", "critical"; #qcom,sensors = <10>; #thermal-sensor-cells = <1>; }; tsens0: thermal-sensor@c263000 { compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; reg = <0x0 0x0c263000 0x0 0x1000>, <0x0 0x0c222000 0x0 0x1000>; interrupts = , ; interrupt-names = "uplow", "critical"; #qcom,sensors = <10>; #thermal-sensor-cells = <1>; }; tsens1: thermal-sensor@c265000 { compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; reg = <0x0 0x0c265000 0x0 0x1000>, <0x0 0x0c223000 0x0 0x1000>; interrupts = , ; interrupt-names = "uplow", "critical"; #qcom,sensors = <10>; #thermal-sensor-cells = <1>; }; aoss_qmp: power-management@c300000 { compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; }; sram@c3f0000 { compatible = "qcom,rpmh-stats"; reg = <0x0 0x0c3f0000 0x0 0x400>; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x1100>, <0x0 0x0c600000 0x0 0x2000000>, <0x0 0x0e600000 0x0 0x100000>, <0x0 0x0e700000 0x0 0xa0000>, <0x0 0x0c40a000 0x0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; qcom,channel = <0>; qcom,ee = <0>; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "periph_irq"; interrupt-controller; #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <0>; }; tlmm: pinctrl@f100000 { compatible = "qcom,qcs8300-tlmm"; reg = <0x0 0x0f100000 0x0 0x300000>; interrupts = ; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&tlmm 0 0 134>; interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; hs0_mi2s_active: hs0-mi2s-active-state { pins = "gpio106", "gpio107", "gpio108", "gpio109"; function = "hs0_mi2s"; drive-strength = <8>; bias-disable; }; mi2s1_active: mi2s1-active-state { data0-pins { pins = "gpio100"; function = "mi2s1_data0"; drive-strength = <8>; bias-disable; }; data1-pins { pins = "gpio101"; function = "mi2s1_data1"; drive-strength = <8>; bias-disable; }; sclk-pins { pins = "gpio98"; function = "mi2s1_sck"; drive-strength = <8>; bias-disable; }; ws-pins { pins = "gpio99"; function = "mi2s1_ws"; drive-strength = <8>; bias-disable; }; }; qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins = "gpio17", "gpio18"; function = "qup0_se0"; }; qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio19", "gpio20"; function = "qup0_se1"; }; qup_i2c2_data_clk: qup-i2c2-data-clk-state { pins = "gpio33", "gpio34"; function = "qup0_se2"; }; qup_i2c3_data_clk: qup-i2c3-data-clk-state { pins = "gpio25", "gpio26"; function = "qup0_se3"; }; qup_i2c4_data_clk: qup-i2c4-data-clk-state { pins = "gpio29", "gpio30"; function = "qup0_se4"; }; qup_i2c5_data_clk: qup-i2c5-data-clk-state { pins = "gpio21", "gpio22"; function = "qup0_se5"; }; qup_i2c6_data_clk: qup-i2c6-data-clk-state { pins = "gpio80", "gpio81"; function = "qup0_se6"; }; qup_i2c8_data_clk: qup-i2c8-data-clk-state { pins = "gpio37", "gpio38"; function = "qup1_se0"; }; qup_i2c9_data_clk: qup-i2c9-data-clk-state { pins = "gpio39", "gpio40"; function = "qup1_se1"; }; qup_i2c10_data_clk: qup-i2c10-data-clk-state { pins = "gpio84", "gpio85"; function = "qup1_se2"; }; qup_i2c11_data_clk: qup-i2c11-data-clk-state { pins = "gpio41", "gpio42"; function = "qup1_se3"; }; qup_i2c12_data_clk: qup-i2c12-data-clk-state { pins = "gpio45", "gpio46"; function = "qup1_se4"; }; qup_i2c13_data_clk: qup-i2c13-data-clk-state { pins = "gpio49", "gpio50"; function = "qup1_se5"; }; qup_i2c14_data_clk: qup-i2c14-data-clk-state { pins = "gpio89", "gpio90"; function = "qup1_se6"; }; qup_i2c15_data_clk: qup-i2c15-data-clk-state { pins = "gpio91", "gpio92"; function = "qup1_se7"; }; qup_i2c16_data_clk: qup-i2c16-data-clk-state { pins = "gpio10", "gpio11"; function = "qup2_se0"; }; qup_spi0_data_clk: qup-spi0-data-clk-state { pins = "gpio17", "gpio18", "gpio19"; function = "qup0_se0"; }; qup_spi0_cs: qup-spi0-cs-state { pins = "gpio20"; function = "qup0_se0"; }; qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { pins = "gpio20"; function = "gpio"; }; qup_spi1_data_clk: qup-spi1-data-clk-state { pins = "gpio19", "gpio20", "gpio17"; function = "qup0_se1"; }; qup_spi1_cs: qup-spi1-cs-state { pins = "gpio18"; function = "qup0_se1"; }; qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { pins = "gpio18"; function = "gpio"; }; qup_spi2_data_clk: qup-spi2-data-clk-state { pins = "gpio33", "gpio34", "gpio35"; function = "qup0_se2"; }; qup_spi2_cs: qup-spi2-cs-state { pins = "gpio36"; function = "qup0_se2"; }; qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { pins = "gpio36"; function = "gpio"; }; qup_spi3_data_clk: qup-spi3-data-clk-state { pins = "gpio25", "gpio26", "gpio27"; function = "qup0_se3"; }; qup_spi3_cs: qup-spi3-cs-state { pins = "gpio28"; function = "qup0_se3"; }; qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { pins = "gpio28"; function = "gpio"; }; qup_spi4_data_clk: qup-spi4-data-clk-state { pins = "gpio29", "gpio30", "gpio31"; function = "qup0_se4"; }; qup_spi4_cs: qup-spi4-cs-state { pins = "gpio32"; function = "qup0_se4"; }; qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { pins = "gpio32"; function = "gpio"; }; qup_spi5_data_clk: qup-spi5-data-clk-state { pins = "gpio21", "gpio22", "gpio23"; function = "qup0_se5"; }; qup_spi5_cs: qup-spi5-cs-state { pins = "gpio24"; function = "qup0_se5"; }; qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { pins = "gpio24"; function = "gpio"; }; qup_spi6_data_clk: qup-spi6-data-clk-state { pins = "gpio80", "gpio81", "gpio82"; function = "qup0_se6"; }; qup_spi6_cs: qup-spi6-cs-state { pins = "gpio83"; function = "qup0_se6"; }; qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { pins = "gpio83"; function = "gpio"; }; qup_spi8_data_clk: qup-spi8-data-clk-state { pins = "gpio37", "gpio38", "gpio39"; function = "qup1_se0"; }; qup_spi8_cs: qup-spi8-cs-state { pins = "gpio40"; function = "qup1_se0"; }; qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { pins = "gpio40"; function = "gpio"; }; qup_spi9_data_clk: qup-spi9-data-clk-state { pins = "gpio39", "gpio40", "gpio37"; function = "qup1_se1"; }; qup_spi9_cs: qup-spi9-cs-state { pins = "gpio38"; function = "qup1_se1"; }; qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { pins = "gpio38"; function = "gpio"; }; qup_spi10_data_clk: qup-spi10-data-clk-state { pins = "gpio84", "gpio85", "gpio86"; function = "qup1_se2"; }; qup_spi10_cs: qup-spi10-cs-state { pins = "gpio87"; function = "qup1_se2"; }; qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { pins = "gpio87"; function = "gpio"; }; qup_spi12_data_clk: qup-spi12-data-clk-state { pins = "gpio45", "gpio46", "gpio47"; function = "qup1_se4"; }; qup_spi12_cs: qup-spi12-cs-state { pins = "gpio48"; function = "qup1_se4"; }; qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { pins = "gpio48"; function = "gpio"; }; qup_spi13_data_clk: qup-spi13-data-clk-state { pins = "gpio49", "gpio50", "gpio51"; function = "qup1_se5"; }; qup_spi13_cs: qup-spi13-cs-state { pins = "gpio52"; function = "qup1_se5"; }; qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { pins = "gpio52"; function = "gpio"; }; qup_spi14_data_clk: qup-spi14-data-clk-state { pins = "gpio89", "gpio90", "gpio91"; function = "qup1_se6"; }; qup_spi14_cs: qup-spi14-cs-state { pins = "gpio92"; function = "qup1_se6"; }; qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { pins = "gpio92"; function = "gpio"; }; qup_spi15_data_clk: qup-spi15-data-clk-state { pins = "gpio91", "gpio92", "gpio89"; function = "qup1_se7"; }; qup_spi15_cs: qup-spi15-cs-state { pins = "gpio90"; function = "qup1_se7"; }; qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { pins = "gpio90"; function = "gpio"; }; qup_spi16_data_clk: qup-spi16-data-clk-state { pins = "gpio10", "gpio11", "gpio12"; function = "qup2_se0"; }; qup_spi16_cs: qup-spi16-cs-state { pins = "gpio13"; function = "qup2_se0"; }; qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { pins = "gpio13"; function = "gpio"; }; qup_uart0_cts: qup-uart0-cts-state { pins = "gpio17"; function = "qup0_se0"; }; qup_uart0_rts: qup-uart0-rts-state { pins = "gpio18"; function = "qup0_se0"; }; qup_uart0_tx: qup-uart0-tx-state { pins = "gpio19"; function = "qup0_se0"; }; qup_uart0_rx: qup-uart0-rx-state { pins = "gpio20"; function = "qup0_se0"; }; qup_uart1_cts: qup-uart1-cts-state { pins = "gpio19"; function = "qup0_se1"; }; qup_uart1_rts: qup-uart1-rts-state { pins = "gpio20"; function = "qup0_se1"; }; qup_uart1_tx: qup-uart1-tx-state { pins = "gpio17"; function = "qup0_se1"; }; qup_uart1_rx: qup-uart1-rx-state { pins = "gpio18"; function = "qup0_se1"; }; qup_uart2_cts: qup-uart2-cts-state { pins = "gpio33"; function = "qup0_se2"; }; qup_uart2_rts: qup-uart2-rts-state { pins = "gpio34"; function = "qup0_se2"; }; qup_uart2_tx: qup-uart2-tx-state { pins = "gpio35"; function = "qup0_se2"; }; qup_uart2_rx: qup-uart2-rx-state { pins = "gpio36"; function = "qup0_se2"; }; qup_uart3_cts: qup-uart3-cts-state { pins = "gpio25"; function = "qup0_se3"; }; qup_uart3_rts: qup-uart3-rts-state { pins = "gpio26"; function = "qup0_se3"; }; qup_uart3_tx: qup-uart3-tx-state { pins = "gpio27"; function = "qup0_se3"; }; qup_uart3_rx: qup-uart3-rx-state { pins = "gpio28"; function = "qup0_se3"; }; qup_uart4_cts: qup-uart4-cts-state { pins = "gpio29"; function = "qup0_se4"; }; qup_uart4_rts: qup-uart4-rts-state { pins = "gpio30"; function = "qup0_se4"; }; qup_uart4_tx: qup-uart4-tx-state { pins = "gpio31"; function = "qup0_se4"; }; qup_uart4_rx: qup-uart4-rx-state { pins = "gpio32"; function = "qup0_se4"; }; qup_uart5_cts: qup-uart5-cts-state { pins = "gpio21"; function = "qup0_se5"; }; qup_uart5_rts: qup-uart5-rts-state { pins = "gpio22"; function = "qup0_se5"; }; qup_uart5_tx: qup-uart5-tx-state { pins = "gpio23"; function = "qup0_se5"; }; qup_uart5_rx: qup-uart5-rx-state { pins = "gpio23"; function = "qup0_se5"; }; qup_uart6_cts: qup-uart6-cts-state { pins = "gpio80"; function = "qup0_se6"; }; qup_uart6_rts: qup-uart6-rts-state { pins = "gpio81"; function = "qup0_se6"; }; qup_uart6_tx: qup-uart6-tx-state { pins = "gpio82"; function = "qup0_se6"; }; qup_uart6_rx: qup-uart6-rx-state { pins = "gpio83"; function = "qup0_se6"; }; qup_uart7_tx: qup-uart7-tx-state { pins = "gpio43"; function = "qup0_se7"; }; qup_uart7_rx: qup-uart7-rx-state { pins = "gpio44"; function = "qup0_se7"; }; qup_uart8_cts: qup-uart8-cts-state { pins = "gpio37"; function = "qup1_se0"; }; qup_uart8_rts: qup-uart8-rts-state { pins = "gpio38"; function = "qup1_se0"; }; qup_uart8_tx: qup-uart8-tx-state { pins = "gpio39"; function = "qup1_se0"; }; qup_uart8_rx: qup-uart8-rx-state { pins = "gpio40"; function = "qup1_se0"; }; qup_uart9_cts: qup-uart9-cts-state { pins = "gpio39"; function = "qup1_se1"; }; qup_uart9_rts: qup-uart9-rts-state { pins = "gpio40"; function = "qup1_se1"; }; qup_uart9_tx: qup-uart9-tx-state { pins = "gpio37"; function = "qup1_se1"; }; qup_uart9_rx: qup-uart9-rx-state { pins = "gpio38"; function = "qup1_se1"; }; qup_uart10_cts: qup-uart10-cts-state { pins = "gpio84"; function = "qup1_se2"; }; qup_uart10_rts: qup-uart10-rts-state { pins = "gpio85"; function = "qup1_se2"; }; qup_uart10_tx: qup-uart10-tx-state { pins = "gpio86"; function = "qup1_se2"; }; qup_uart10_rx: qup-uart10-rx-state { pins = "gpio87"; function = "qup1_se2"; }; qup_uart11_tx: qup-uart11-tx-state { pins = "gpio41"; function = "qup1_se3"; }; qup_uart11_rx: qup-uart11-rx-state { pins = "gpio42"; function = "qup1_se3"; }; qup_uart12_cts: qup-uart12-cts-state { pins = "gpio45"; function = "qup1_se4"; }; qup_uart12_rts: qup-uart12-rts-state { pins = "gpio46"; function = "qup1_se4"; }; qup_uart12_tx: qup-uart12-tx-state { pins = "gpio47"; function = "qup1_se4"; }; qup_uart12_rx: qup-uart12-rx-state { pins = "gpio48"; function = "qup1_se4"; }; qup_uart13_cts: qup-uart13-cts-state { pins = "gpio49"; function = "qup1_se5"; }; qup_uart13_rts: qup-uart13-rts-state { pins = "gpio50"; function = "qup1_se5"; }; qup_uart13_tx: qup-uart13-tx-state { pins = "gpio51"; function = "qup1_se5"; }; qup_uart13_rx: qup-uart13-rx-state { pins = "gpio52"; function = "qup1_se5"; }; qup_uart14_cts: qup-uart14-cts-state { pins = "gpio89"; function = "qup1_se6"; }; qup_uart14_rts: qup-uart14-rts-state { pins = "gpio90"; function = "qup1_se6"; }; qup_uart14_tx: qup-uart14-tx-state { pins = "gpio91"; function = "qup1_se6"; }; qup_uart14_rx: qup-uart14-rx-state { pins = "gpio92"; function = "qup1_se6"; }; qup_uart15_cts: qup-uart15-cts-state { pins = "gpio91"; function = "qup1_se7"; }; qup_uart15_rts: qup-uart15-rts-state { pins = "gpio92"; function = "qup1_se7"; }; qup_uart15_tx: qup-uart15-tx-state { pins = "gpio89"; function = "qup1_se7"; }; qup_uart15_rx: qup-uart15-rx-state { pins = "gpio90"; function = "qup1_se7"; }; qup_uart16_cts: qup-uart16-cts-state { pins = "gpio10"; function = "qup2_se0"; }; qup_uart16_rts: qup-uart16-rts-state { pins = "gpio11"; function = "qup2_se0"; }; qup_uart16_tx: qup-uart16-tx-state { pins = "gpio12"; function = "qup2_se0"; }; qup_uart16_rx: qup-uart16-rx-state { pins = "gpio13"; function = "qup2_se0"; }; sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; drive-strength = <16>; bias-disable; }; cmd-pins { pins = "sdc1_cmd"; drive-strength = <10>; bias-pull-up; }; data-pins { pins = "sdc1_data"; drive-strength = <10>; bias-pull-up; }; rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; sdc1_state_off: sdc1-off-state { clk-pins { pins = "sdc1_clk"; drive-strength = <2>; bias-bus-hold; }; cmd-pins { pins = "sdc1_cmd"; drive-strength = <2>; bias-bus-hold; }; data-pins { pins = "sdc1_data"; drive-strength = <2>; bias-bus-hold; }; rclk-pins { pins = "sdc1_rclk"; bias-bus-hold; }; }; }; sram: sram@146d8000 { compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; reg = <0x0 0x146d8000 0x0 0x1000>; ranges = <0x0 0x0 0x146d8000 0x1000>; #address-cells = <1>; #size-cells = <1>; pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; }; }; apps_smmu: iommu@15000000 { compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; dma-coherent; interrupts = , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; }; pcie_smmu: iommu@15200000 { compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15200000 0x0 0x80000>; #iommu-cells = <2>; #global-interrupts = <2>; dma-coherent; interrupts = , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; }; intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, <0x0 0x17a60000 0x0 0x100000>; interrupts = ; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; }; watchdog@17c10000 { compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; clocks = <&sleep_clk>; interrupts = ; }; timer@17c20000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; ranges = <0x0 0x0 0x0 0x20000000>; #address-cells = <1>; #size-cells = <1>; frame@17c21000 { reg = <0x17c21000 0x1000>, <0x17c22000 0x1000>; frame-number = <0>; interrupts = , ; }; frame@17c23000 { reg = <0x17c23000 0x1000>; frame-number = <1>; interrupts = ; status = "disabled"; }; frame@17c25000 { reg = <0x17c25000 0x1000>; frame-number = <2>; interrupts = ; status = "disabled"; }; frame@17c27000 { reg = <0x17c27000 0x1000>; frame-number = <3>; interrupts = ; status = "disabled"; }; frame@17c29000 { reg = <0x17c29000 0x1000>; frame-number = <4>; interrupts = ; status = "disabled"; }; frame@17c2b000 { reg = <0x17c2b000 0x1000>; frame-number = <5>; interrupts = ; status = "disabled"; }; frame@17c2d000 { reg = <0x17c2d000 0x1000>; frame-number = <6>; interrupts = ; status = "disabled"; }; }; apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; reg = <0x0 0x18200000 0x0 0x10000>, <0x0 0x18210000 0x0 0x10000>, <0x0 0x18220000 0x0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; interrupts = , , ; power-domains = <&system_pd>; label = "apps_rsc"; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , , , ; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; rpmhcc: clock-controller { compatible = "qcom,sa8775p-rpmh-clk"; #clock-cells = <1>; clocks = <&xo_board_clk>; clock-names = "xo"; }; rpmhpd: power-controller { compatible = "qcom,qcs8300-rpmhpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmhpd_opp_table>; rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp-0 { opp-level = ; }; rpmhpd_opp_min_svs: opp-1 { opp-level = ; }; rpmhpd_opp_low_svs: opp-2 { opp-level = ; }; rpmhpd_opp_svs: opp-3 { opp-level = ; }; rpmhpd_opp_svs_l1: opp-4 { opp-level = ; }; rpmhpd_opp_nom: opp-5 { opp-level = ; }; rpmhpd_opp_nom_l1: opp-6 { opp-level = ; }; rpmhpd_opp_nom_l2: opp-7 { opp-level = ; }; rpmhpd_opp_turbo: opp-8 { opp-level = ; }; rpmhpd_opp_turbo_l1: opp-9 { opp-level = ; }; }; }; }; epss_l3_cl0: interconnect@18590000 { compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", "qcom,epss-l3"; reg = <0x0 0x18590000 0x0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #interconnect-cells = <1>; }; cpufreq_hw: cpufreq@18591000 { compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0x0 0x18591000 0x0 0x1000>, <0x0 0x18593000 0x0 0x1000>, <0x0 0x18594000 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; interrupts = , , ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; }; epss_l3_cl1: interconnect@18592000 { compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", "qcom,epss-l3"; reg = <0x0 0x18592000 0x0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #interconnect-cells = <1>; }; remoteproc_gpdsp: remoteproc@20c00000 { compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; reg = <0x0 0x20c00000 0x0 0x10000>; interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, <&smp2p_gpdsp_in 0 0>, <&smp2p_gpdsp_in 1 0>, <&smp2p_gpdsp_in 2 0>, <&smp2p_gpdsp_in 3 0>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd RPMHPD_CX>, <&rpmhpd RPMHPD_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; memory-region = <&gpdsp_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&smp2p_gpdsp_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "gpdsp"; qcom,remote-pid = <17>; }; }; ethernet0: ethernet@23040000 { compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; reg = <0x0 0x23040000 0x0 0x00010000>, <0x0 0x23056000 0x0 0x00000100>; reg-names = "stmmaceth", "rgmii"; interrupts = , ; interrupt-names = "macirq", "sfty"; clocks = <&gcc GCC_EMAC0_AXI_CLK>, <&gcc GCC_EMAC0_SLV_AHB_CLK>, <&gcc GCC_EMAC0_PTP_CLK>, <&gcc GCC_EMAC0_PHY_AUX_CLK>; clock-names = "stmmaceth", "pclk", "ptp_ref", "phyaux"; power-domains = <&gcc GCC_EMAC0_GDSC>; phys = <&serdes0>; phy-names = "serdes"; iommus = <&apps_smmu 0x120 0xf>; dma-coherent; snps,tso; snps,pbl = <32>; rx-fifo-depth = <16384>; tx-fifo-depth = <20480>; status = "disabled"; }; nspa_noc: interconnect@260c0000 { compatible = "qcom,qcs8300-nspa-noc"; reg = <0x0 0x260c0000 0x0 0x16080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; remoteproc_cdsp: remoteproc@26300000 { compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; reg = <0x0 0x26300000 0x0 0x10000>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd RPMHPD_CX>, <&rpmhpd RPMHPD_MXC>, <&rpmhpd RPMHPD_NSP0>; power-domain-names = "cx", "mxc", "nsp"; interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; memory-region = <&cdsp_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&smp2p_cdsp_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "cdsp"; qcom,remote-pid = <5>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; #address-cells = <1>; #size-cells = <0>; compute-cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x19c1 0x0440>, <&apps_smmu 0x1961 0x0400>; dma-coherent; }; compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x19c2 0x0440>, <&apps_smmu 0x1962 0x0400>; dma-coherent; }; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x19c3 0x0440>, <&apps_smmu 0x1963 0x0400>; dma-coherent; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x19c4 0x0440>, <&apps_smmu 0x1964 0x0400>; dma-coherent; }; }; }; }; }; thermal_zones: thermal-zones { aoss-0-thermal { thermal-sensors = <&tsens0 0>; trips { aoss0-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-0-0-0-thermal { thermal-sensors = <&tsens0 1>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-0-1-0-thermal { thermal-sensors = <&tsens0 2>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-0-2-0-thermal { thermal-sensors = <&tsens0 3>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-0-3-0-thermal { thermal-sensors = <&tsens0 4>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; gpuss-0-thermal { thermal-sensors = <&tsens0 5>; trips { gpuss0_alert0: trip-point0 { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; gpuss0-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&gpuss0_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; audio-thermal { thermal-sensors = <&tsens0 6>; trips { audio-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; camss-0-thermal { thermal-sensors = <&tsens0 7>; trips { camss-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; pcie-0-thermal { thermal-sensors = <&tsens0 8>; trips { pcie-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpuss-0-0-thermal { thermal-sensors = <&tsens0 9>; trips { cpuss0-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; aoss-1-thermal { thermal-sensors = <&tsens1 0>; trips { aoss1-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-0-0-1-thermal { thermal-sensors = <&tsens1 1>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-0-1-1-thermal { thermal-sensors = <&tsens1 2>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-0-2-1-thermal { thermal-sensors = <&tsens1 3>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-0-3-1-thermal { thermal-sensors = <&tsens1 4>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; gpuss-1-thermal { thermal-sensors = <&tsens1 5>; trips { gpuss1_alert0: trip-point0 { temperature = <115000>; hysteresis = <5000>; type = "passive"; }; gpuss1-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&gpuss1_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; video-thermal { thermal-sensors = <&tsens1 6>; trips { video-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; camss-1-thermal { thermal-sensors = <&tsens1 7>; trips { camss1-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; pcie-1-thermal { thermal-sensors = <&tsens1 8>; trips { pcie-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpuss-0-1-thermal { thermal-sensors = <&tsens1 9>; trips { cpuss0-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; aoss-2-thermal { thermal-sensors = <&tsens2 0>; trips { aoss2-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-1-0-0-thermal { thermal-sensors = <&tsens2 1>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-1-1-0-thermal { thermal-sensors = <&tsens2 2>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-1-2-0-thermal { thermal-sensors = <&tsens2 3>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-1-3-0-thermal { thermal-sensors = <&tsens2 4>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; nsp-0-0-0-thermal { thermal-sensors = <&tsens2 5>; trips { nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; nsp-0-1-0-thermal { thermal-sensors = <&tsens2 6>; trips { nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; nsp-0-2-0-thermal { thermal-sensors = <&tsens2 7>; trips { nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; ddrss-0-thermal { thermal-sensors = <&tsens2 8>; trips { ddrss-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpuss-1-0-thermal { thermal-sensors = <&tsens2 9>; trips { cpuss1-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; aoss-3-thermal { thermal-sensors = <&tsens3 0>; trips { aoss3-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-1-0-1-thermal { thermal-sensors = <&tsens3 1>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-1-1-1-thermal { thermal-sensors = <&tsens3 2>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-1-2-1-thermal { thermal-sensors = <&tsens3 3>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu-1-3-1-thermal { thermal-sensors = <&tsens3 4>; trips { cpu-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; nsp-0-0-1-thermal { thermal-sensors = <&tsens3 5>; trips { nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; nsp-0-1-1-thermal { thermal-sensors = <&tsens3 6>; trips { nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; nsp-0-2-1-thermal { thermal-sensors = <&tsens3 7>; trips { nsp-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; ddrss-1-thermal { thermal-sensors = <&tsens3 8>; trips { ddrss-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; cpuss-1-1-thermal { thermal-sensors = <&tsens3 9>; trips { cpuss1-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; };